EP0279229A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A graphics display system
Assignee: International Business Machines Corp
•
Filing: 1988-01-26
•
Granted: —
•
Expires: 2008-01-26
Abstract
Abstract A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory.
Inventors
- 👤 Robert Lockwood Mansfield
- 👤 Marc Segre
- 👤 Alexander Koos Spencer
- 👤 Joe Christopher St. Clair
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 23:01
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
105 words
A graphics display system including a receiving circuit for receiving graphics information to be displayed, a memory for storing received graphics information in an array thereof which includes a portion that directly corresponds to the image area for display on a display device connected to the memory, and accessed by an access circuit providing array access during a single memory cycle time, together with a loading circuit connected to the receiving circuit and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle, where N and M are integers each greater than 1.
Claim 2
Dependent Claim
105 words
A graphics display system including a receiving circuit for receiving graphics information to be displayed, a memory for storing received graphics information in an array thereof which includes a portion that directly corresponds to the image area for display on a display device connected to the memory, and accessed by an access circuit providing array access during a single memory cycle time, together with a loading circuit connected to the receiving circuit and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle, where N and M are integers each greater than 1.
Claim 3
Dependent Claim
38 words
A display system as claimed in claim 1, wherein the loading circuit includes a control circuit that provides control signals to the memory that indicate data to be loaded into the N by M portion of the memory.
Claim 4
Dependent Claim
67 words
A display system as claimed in claim 2, including a register that contains the pattern of data to be loaded into the memory, to the contents of which register the control circuit is responsive to generate those control signals which are to be transmitted to the memory whereby the transmitting of the control signals is actually an indication of data pattern to be loaded into the memory.
Claim 5
Dependent Claim
84 words
A display system as claimed in claim 2 or claim 3, wherein there is a plurality of data lines for transmitting data to the memory, a portion of these data lines being interconnected together to provide the same data, the transmission of data on these data lines being regulated by the control signals such that even though data on a specific data line may be available, it will not be transmitted to the memory if the pattern contained in the control register so indicates.
Claim 6
Dependent Claim
45 words
A display system as claimed in claim 4, wherein the control signals include row and column strobes and a write enable signal, the write enable signal being selectively generated to determine which of a predetermined set of data lines will be written to the memory.
Claim 7
Dependent Claim
55 words
A display system as claimed in any preceding claim, wherein the memory array is configured to store data designating characteristics of picture elements for the display using eight bits to describe each picture element and it is the data relating to N by M picture elements that can be accessed in a single memory cycle.
Claim 8
Dependent Claim
40 words
A display system as claimed in any preceding claim, wherein the loading circuit also provides timing signals to the memory that define individual memory access periods during which picture element data can be written to or read from the memory.
Claim 9
Dependent Claim
76 words
A display system as claimed in any preceding claim, adapted to, inter alia, display at least two patterned lines forming an intersection and including: processing means for computing which picture elements in an array of picture elements are to be activated to display the lines; and regulating means for regulating the activation of the picture elements to provide the pattern for the lines including means for providing display pattern continuity along the intersection of the lines.
Claim 10
Dependent Claim
56 words
A display system as claimed in claim 8, wherein the regulating means includes counter means for computing the activation of picture elements according to the pattern, the counter means including a register for storing a pattern count upon the completion of a first line to be used to initiate a pattern computation for the intersecting line.
Claim 11
Dependent Claim
64 words
A display system as claimed in claim 9, further including provision for maintaining pattern continuity along the line portion outside of the predetermined region for display via a continuity register having the boundary of the predetermined region stored therein and means for providing activation of those picture elements only within the predetermined region while providing a pattern computation for the portion not being displayed.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.