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EP0278264A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processing system with overlap bus cycle operations

Assignee: International Business Machines Corp
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Filing: 1988-01-19
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Granted: —
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Expires: 2008-01-19
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Abstract

Abstract A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires only a single device to regulate communication between devices at any one time. This regulating device is termed the bus master and the remaining devices are termed slaves. This protocol provides the capability for a slave device to indicate to the bus master that a new bus master is to be designated for a temporary communications. This communications with a different bus master then overlaps within the bus cycles of the designated bus master.

Inventors

  • 👤 Harrell Hoffman
  • 👤 Charles Wright

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-24 14:27
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 90 words
A data processing system including at least three devices connected to an asynchronous communications bus for intercommunications between said devices, said communications bus including a protocol requiring only a single device to regulate communication between devices at any one time, characterised in that said bus comprises: means for designating a first device to regulate communications on said bus; and means for another device to request said first device to designate a different device to temporarily regulate communications and to return bus regulation to the first device after said tempo­rary communication.
Claim 2
Dependent Claim 90 words
A data processing system including at least three devices connected to an asynchronous communications bus for intercommunications between said devices, said communications bus including a protocol requiring only a single device to regulate communication between devices at any one time, characterised in that said bus comprises: means for designating a first device to regulate communications on said bus; and means for another device to request said first device to designate a different device to temporarily regulate communications and to return bus regulation to the first device after said tempo­rary communication.
Claim 3
Dependent Claim 36 words
A data processing system according to Claim 1 wherein said other device includes means to request said first device to temporarily designate a second device to regulate communications between said second device and said other device.
Claim 4
Dependent Claim 29 words
A data processing system according to Claim 2 wherein said communication bus includes means in said designated devices to provide at least one communications timing signal on said bus.
Claim 5
Dependent Claim 28 words
A data processing system according to Claim 3 wherein said timing means in said designated first device cease providing said timing signal upon designation of said second device.
Claim 6
Dependent Claim 122 words
A data processing system including at least a first, second and third device connected to an asynchronous communications bus for intercommunications between said devices, said communications bus including an arbitration circuit to designate a device as a first bus master to regulate communication between devices for a communications period and designating remaining devices as slave devices, characterised in that said bus comprises: means connected to the slave devices for providing a signal indicating that a new bus master is to be designated temporarily for providing communications with the signaling device; and means for redesignating another of said devices to be a new bus master and remaining devices as slave devices in response to said signal without any communications with said arbitration circuit.
Claim 7
Dependent Claim 122 words
A data processing system including at least a first, second and third device connected to an asynchronous communications bus for intercommunications between said devices, said communications bus including an arbitration circuit to designate a device as a first bus master to regulate communication between devices for a communications period and designating remaining devices as slave devices, characterised in that said bus comprises: means connected to the slave devices for providing a signal indicating that a new bus master is to be designated temporarily for providing communications with the signaling device; and means for redesignating another of said devices to be a new bus master and remaining devices as slave devices in response to said signal without any communications with said arbitration circuit.
Claim 8
Dependent Claim 53 words
A data processing system according to Claim 5 wherein said bus includes a plurality of timing means connected to all potential bus master devices for providing at least one communications timing signal on said bus, said timing means including means for stopping the timing signal when its connected device is not bus master.
Claim 9
Dependent Claim 30 words
A data processing system according to Claim 6 wherein said signalling slave device provides a signal to the first bus master indicating the request to designate the new bus master.
Claim 10
Dependent Claim 38 words
A data processing system according to Claim 7 wherein said first bus master includes means to provide a second signal on said bus indicating to the new bus master that the first bus master is relinquishing bus control.
Claim 11
Dependent Claim 51 words
A data processing system according to Claim 8 wherein said new bus master provides a third signal on said bus indicating to the first bus master and the signalling slave device that the new bus master has control of the bus and the communications with the signalling slave is to begin.
Claim 12
Dependent Claim 44 words
A data processing system according to Claim 9 wherein said new bus master removes the third signal upon completion of communications with the signalling slave indicating to the first bus master that control of the bus is being returned to the first bus master.

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