EP0276087A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improved multilayer interconnection for integrated circuit structure having two or more conductive metal layers and method of making same
Assignee: Advanced Micro Devices Inc
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Filing: 1988-01-14
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Granted: —
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Expires: 2008-01-14
Abstract
Abstract Construction of a novel multilayer conductive interconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer (40) which may be in contact with an underlying silicon substrate (10) and comprising a material selected from the class consisting of TiW and TiN; an intermediate layer (50) of conductive metal such as an aluminum base metal; and an upper barrier layer (60) which may be in contact with a second aluminum base metal layer (80) and which is selected from the class consisting of TiW, TiN, MoSix and TaSi where x equals 2 or more.
Inventors
- 👤 Krishna Shankar
- 👤 Ram Ramani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 00:00
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
171 words
An improved integrated circuit structure comprising a multilayer conductive interconnection layer formed between the substrate and a second metal layer, and having reduced diffusion of conductive metal and silicon therebetween and reduced formation of spikes or hillocks, said structure comprising: a) a silicon substrate having at least one doped region and oxide portions adjacent said doped region; b) a lower conductive barrier layer in electrical contact with said doped region of said substrate comprising a material selected from the class consisting of TiW and TiN; c) an intermediate layer of conductive metal formed over and in contact with said lower conductive layer; d) an upper conductive barrier layer formed on said intermediate layer and selected from the class consisting of TiW, TiN, MoSi x , and TaSi x wherein x equals 2 or more; said lower layer, intermediate layer, and upper layer functioning together as a multilayer interconnection layer; and e) a second metal layer in said structure having at lest one portion thereof in electrical contact with said interconnection layer.
Claim 2
Dependent Claim
171 words
An improved integrated circuit structure comprising a multilayer conductive interconnection layer formed between the substrate and a second metal layer, and having reduced diffusion of conductive metal and silicon therebetween and reduced formation of spikes or hillocks, said structure comprising: a) a silicon substrate having at least one doped region and oxide portions adjacent said doped region; b) a lower conductive barrier layer in electrical contact with said doped region of said substrate comprising a material selected from the class consisting of TiW and TiN; c) an intermediate layer of conductive metal formed over and in contact with said lower conductive layer; d) an upper conductive barrier layer formed on said intermediate layer and selected from the class consisting of TiW, TiN, MoSi x , and TaSi x wherein x equals 2 or more; said lower layer, intermediate layer, and upper layer functioning together as a multilayer interconnection layer; and e) a second metal layer in said structure having at lest one portion thereof in electrical contact with said interconnection layer.
Claim 3
Dependent Claim
21 words
The structure of claim 1 wherein said intermediate layer of conductive metal comprises a 2500-3500Å layer of an aluminum base metal.
Claim 4
Dependent Claim
43 words
The structure of claim 2 wherein said lower conductive barrier layer comprises a 800-1500Å layer to inhibit the diffusion of silicon therethrough into said intermediate aluminum base metal layer and the diffusion of aluminum from said intermediate layer therethrough into said silicon substrate.
Claim 5
Dependent Claim
25 words
The structure of claim 3 wherein said lower conductive barrier layer is further characterized by a 20-50Å layer of oxide on the upper surface thereof.
Claim 6
Dependent Claim
41 words
The structure of claim 4 wherein said lower barrier layer is further characterized by oxide present between the grain boundaries therein formed by exposed said layer to the atmosphere after the formation thereof and prior to forming said intermediate layer thereon.
Claim 7
Dependent Claim
37 words
The structure of claim 3 wherein said upper conductive barrier layer comprises a 800-1200Å layer which will inhibit the diffusion of aluminum therethrough from said intermediate layer to form hillocks or spikes passing into other layers thereover.
Claim 8
Dependent Claim
44 words
The structure of claim 6 wherein said doped silicon region in said substrate has a metal silicide layer formed in the surface thereof beneath said lower conductive barrier layer to enhance the conductivity between said doped region in said substrate and said interconnection layer.
Claim 9
Independent Claim
169 words
A method of forming an improved integrated circuit structure comprising a novel multilayer conductive interconnection layer formed between the substrate and a second metal layer, and having reduced diffusion of conductive metal and silicon therebetween and reduced formation of spikes or hillocks, said method comprising: a) forming a lower conductive barrier layer over a silicon substrate in electrical contact with a doped region of said substrate using a a material selected from the class consisting of TiW and TiN; b) forming an intermediate layer of conductive metal over and in contact with said lower conductive barrier layer; c) forming an upper conductive barrer layer on said intermediate layer using material selected from the class consisting of TiW, MoSi x , TaSi x , and TiN wherein x equals 2 or more; said lower layer, intermediate layer, and upper layer functioning together as a multilayer interconnection layer; and d) forming a second metal layer over said structure having at least one portion thereof in electrical contact with said interconnection layer.
Claim 10
Independent Claim
169 words
A method of forming an improved integrated circuit structure comprising a novel multilayer conductive interconnection layer formed between the substrate and a second metal layer, and having reduced diffusion of conductive metal and silicon therebetween and reduced formation of spikes or hillocks, said method comprising: a) forming a lower conductive barrier layer over a silicon substrate in electrical contact with a doped region of said substrate using a a material selected from the class consisting of TiW and TiN; b) forming an intermediate layer of conductive metal over and in contact with said lower conductive barrier layer; c) forming an upper conductive barrer layer on said intermediate layer using material selected from the class consisting of TiW, MoSi x , TaSi x , and TiN wherein x equals 2 or more; said lower layer, intermediate layer, and upper layer functioning together as a multilayer interconnection layer; and d) forming a second metal layer over said structure having at least one portion thereof in electrical contact with said interconnection layer.
Claim 11
Dependent Claim
38 words
The method of claim 8 including the further step of forming a first oxide layer over said substrate having an opening therein to expose said doped region of said substrate before forming said lower conductive barrier layer thereon.
Claim 12
Dependent Claim
84 words
The method of claim 8 including the further steps of forming a layer over said first oxide and said exposed doped silicon substrate of a metal capable of reacting with said silicon to form a metal silicide, heating said structure to a temperature of about 500-700°C to sinter said metal and form said metal silicide over and in the surface of said doped silicon substrate, and removing unreacted portions of said metal on said first oxide layer before forming said lower conductive barrier layer.
Claim 13
Dependent Claim
49 words
The method of claim 9 wherein said step of forming said lower conductive barrier layer using a material selected from the class consisting of TiW and TiN further comprises sputtering from 800-1500Å of TiW onto said structure from a target containing about 10-30 wt.% titanium and 70-90 wt.% tungsten.
Claim 14
Dependent Claim
39 words
The method of claim 11 wherein said sputtering is carried out in an argon atmosphere of from about 5 to 15 milliTorr while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C.
Claim 15
Dependent Claim
70 words
The method of claim 9 wherein said step of forming said lower conductive barrier layer using a material selected from the class consisting of TiW and TiN further comprises sputtering from 800-1500Å of TiN onto said structure from a TiN composite target in an argon atmosphere of from about 5 to 15 milliTorr while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C.
Claim 16
Dependent Claim
101 words
The method of claim 9 wherein said step of forming said lower conductive barrier layer using a material selected from the class consisting of TiW and TiN further comprises a first step of sputtering from 200-800Å of titanium onto said structure from a titanium target in an argon atmosphere of from about 5 to 15 milliTorr while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C and a second step of reactively sputtering titanium nitride (TiN) onto said titanium layer under the same reaction conditions to form said TiN layer on said silicon substrate.
Claim 17
Dependent Claim
105 words
The method of claim 14 wherein said first step of applying said titanium layer to said silicon substrate is followed by a rapid anneal comprising heating the structure up to a temperature of from about 600-800°C within a period of about 10 seconds and then maintaining the structure at this temperature for a period of from about 30 seconds to 1 minutes in a nitrogen atmosphere to clean the silicon surface and cause at least a portion of said titanium to react with said silicon to form a titanium silicide thus enabling good electrical contact to silicon while forming a TiN barrier at the surface.
Claim 18
Dependent Claim
48 words
The method of claim 9 wherein said step of forming said lower barrier layer is followed by the step of exposing said newly formed lower barrier layer to air to oxidize at least the surface of said lower barrier layer to form a 20-50Å layer of oxide thereon.
Claim 19
Dependent Claim
41 words
The method of claim 9 wherein said step of forming said intermediate layer of conductive metal over and in contact with said lower conductive barrier layer further comprises depositing a 2500-3500Å layer of an aluminum-based metal over said lower barrier layer.
Claim 20
Dependent Claim
54 words
The method of claim 9 wherein said step of forming said upper barrier layer further includes sputtering from 800-1200Å of said material over said intermediate layer in an argon atmosphere of from about 5 to 15 milliTorr while maintaining a temperature of from at least about 100°C up to a temperature not exceeding 400°C.
Claim 21
Dependent Claim
53 words
The method of claim 9 including the further steps of forming a second oxide layer over said interconnection layer, patterning said second oxide layer to expose at least a portion of said inter-connection layer, and cleaning the surface of said interconnection layer to remove oxides thereon before forming said second metal layer thereover.
Claim 22
Independent Claim
321 words
A method forming an improved integrated circuit structure comprising a novel multilayer conductive interconnection layer formed between a silicon substrate and a second metal layer, and characterized by reduced diffusion of conductive metal and silicon therebetween and reduced formation of spikes or hillocks, said method comprising: a) forming a first oxide layer over said silicon substrate having an opening therein to expose a doped region of said silicon substrate; b) sputtering a 800-1500Å thick lower conductive barrier layer over said silicon substrate in electrical contact with said doped region of said substrate in a nonreactive atmosphere at about 5 to 15 milliTorr using a material selected from the classes consisting of TiW and TiN while maintaining a temperature of from 100-400°C; c) exposing said lower conductive barrier layer to air to form a 20-50Å oxide layer thereon; d) forming a 2500-3500Å intermediate layer of an aluminum-base metal over and in electrical contact with said lower conductive barrier layer through said oxide layer; e) sputtering a 800-1200Å thick upper conductive barrier layer on said intermediate layer in a nonreactive atmosphere at about 5 to 15 milliTorr using material selected from the class consisting of TiW, TiN, MoSi x , and TaSi x where x equals 2 or more, while maintaining a temperature of from 100-400°C; said lower layer, intermediate layer, and upper layer functioning together as a multilayer interconnection layer; f) patterning said interconnection layer to form a preselected pattern of conductive lines over said substrate and said first oxide thereon; g) forming a second oxide layer over said interconnection layer; h) patterning said second oxide layer to expose a portion of said interconnection layer; i) cleaning said exposed portion of said interconnection layer to remove oxide formed thereon during said formation of said second oxide layer; and j) forming a second aluminum base metal layer over said structure having at least one portion thereof in electrical contact with said interconnection layer.
Claim 23
Independent Claim
321 words
A method forming an improved integrated circuit structure comprising a novel multilayer conductive interconnection layer formed between a silicon substrate and a second metal layer, and characterized by reduced diffusion of conductive metal and silicon therebetween and reduced formation of spikes or hillocks, said method comprising: a) forming a first oxide layer over said silicon substrate having an opening therein to expose a doped region of said silicon substrate; b) sputtering a 800-1500Å thick lower conductive barrier layer over said silicon substrate in electrical contact with said doped region of said substrate in a nonreactive atmosphere at about 5 to 15 milliTorr using a material selected from the classes consisting of TiW and TiN while maintaining a temperature of from 100-400°C; c) exposing said lower conductive barrier layer to air to form a 20-50Å oxide layer thereon; d) forming a 2500-3500Å intermediate layer of an aluminum-base metal over and in electrical contact with said lower conductive barrier layer through said oxide layer; e) sputtering a 800-1200Å thick upper conductive barrier layer on said intermediate layer in a nonreactive atmosphere at about 5 to 15 milliTorr using material selected from the class consisting of TiW, TiN, MoSi x , and TaSi x where x equals 2 or more, while maintaining a temperature of from 100-400°C; said lower layer, intermediate layer, and upper layer functioning together as a multilayer interconnection layer; f) patterning said interconnection layer to form a preselected pattern of conductive lines over said substrate and said first oxide thereon; g) forming a second oxide layer over said interconnection layer; h) patterning said second oxide layer to expose a portion of said interconnection layer; i) cleaning said exposed portion of said interconnection layer to remove oxide formed thereon during said formation of said second oxide layer; and j) forming a second aluminum base metal layer over said structure having at least one portion thereof in electrical contact with said interconnection layer.
References Cited (Backward Citations)
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