Digital signal switch

Claim 2

A switch according to claim 1 in which the means for receiving each bit of an input bit packet comprises buffer means for holding a plurality of bits.

Claim 3

A switch according to claim 2 in which said buffer means has a bit capacity to hold at least one bit packet of said first type, whereby small differences in bit frequency between input bit packets and output bit packets may be accommodated without loss of data in the switch.

Claim 4

A switch according to claim 3 in which said buffer means has a bit capacity of at least ten bits.

Claim 5

A switch according to any one of the preceding claims in which said connecting means further comprises a plurality of signal paths between the plurality of inputs and outputs, each path having a selector with latch means to determine which input/output pair is to be connected through that selector.

Claim 6

A switch according to claim 5 in which each signal path further comprises synchronising means for sampling input signals at a frequency higher than the bit frequency of the input signal in order to detect a leading edge of a start bit of a packet and supplying a synchronised signal after a controlled time interval from detection of said leading edge in order to provide a true indication of the bit pattern in an input packet regardless of any phase difference between said clock means and the phase of input packet signals.

Claim 7

A switch according to claims 3 and 5 in which each signal path includes a first in first out buffer having input counter means for clocking data into the buffer and output counter means for clocking data out of said buffer.

Claim 8

A switch according to claims 6 and 7 in which said input counter is arranged to receive clock signals from said synchronising means.

Claim 9

A switch according to any one of the preceding claims including a communication interface to enable communication between said switch and a controlling device, such as a microcomputer, said communication interface being connected to said connecting means in order to set a desired configuration for the switch interconnections.

Claim 10

A switch according to claim 9 in which said communication interface comprises an output channel for outputting data and an input channel for receiving data, the output channel comprising (a) an output terminal for connection to an external unidirectional communication line so as to transmit data bits serially along the line, and (b) packet generator means arranged to generate and supply to the output terminal serial bit packets comprising data packets of a first format for conveying data and acknowledgement packets of a second format to indicate receipt of a data packet, said input channel comprising (c) an input terminal for connection to an external unidirectional communication line so as to receive data bits serially along the line, and (d) packet decoding means for receiving serial bit packets from said input terminal and detecting whether the packet is of the first format or of the second format; said interface including control means connected to said packet generator means and said packet decoding means and responsive to the output of a packet by the output channel or receipt of a packet by the input channel to cause the packet generator means to output an acknowledgement packet in response to receipt of the data packet by the input channel and after output of a data packet to prevent output of a further data packet until the input channel has received an acknowledgement packet.

Claim 11

A network of interconnected digital devices including a plurality of microcomputers, said devices being interconnected by at least one switch device and arranged to communicate with each other by serial bit packets of two types, a first type being data packet of a first format commencing with a start bit and a second type being an acknowledgement packet of a second format commencing with a start bit, said switch having a plurality of inputs, a plurality of outputs, and connecting means for selectively interconnecting said inputs and outputs, said connecting means having bit detecting means for detecting a start bit of a serial bit packet which is input to the switch, decoding means for determining whether the packet is of the first of second type, clock means providing timing signals, means for receiving each bit of an input bit packet which is received at an input and under control of said clock means generating as an output an output bit packet having bit signals corresponding to the bits of the input bit packet.

Claim 12

A network according to claim 11 in which each device is connected to a said switch device by a communication interface which comprises an output channel for outputting data and an input channel for receiving data, the output channel comprising (a) an output terminal for connection to an external unidirectional communication line so as to transmit data bits serially along the line, and (b) packet generator means arranged to generate and supply to the output terminal serial bit packets comprising data packets of a first format for conveying data and acknowledgement packets of a second format to indicate receipt of a data packet, said input channel comprising (c) an input terminal for connection to an external unidirectional communication line so as to receive data bits serially along the line, and (d) packet decoding means for receiving serial bit packets from said input terminal and detecting whether the packet is of the first format or of the second format; said interface including control means connected to said packet generator means and said packet decoding means and responsive to the output of a packet by the output channel or receipt of a packet by the input channel to cause the packet generator means to output an acknowledgement packet in response to receipt of the data packet by the input channel and after output of a data packet to prevent output of a further data packet until the input channel has received an acknowledgement packet.

Claim 13

A network according to claim 11 or 12 in which the or each switch device includes buffer means for holding a plurality of signal bits received by the switch, said buffer means having a bit capacity to hold at least one bit packet of said first type.

Claim 14

A network of interconnected digital devices as claimed in any one of claims 11 to 13 in which the configuration of the network is determined by one or more switch devices as claimed in any one of claims 1 to 10.

Claim 16

A method according to claim 15 including sampling input signals at each input of a switch device at a frequency higher than the bit frequency of the input signal in order to detect a leading edge of a start bit of a packet and supplying a synchronised signal after a controlled time interval from detection of said leading edge in order to provide an indication of the bit pattern in an input packet.

Claim 17

A method according to claim 15 or claim 16 including setting a plurality of interconnections within the switch device by communication of signals from a communication interface on a microcomputer with a connected communication interface on said switch device.