Patent US1860710A successfully refreshed from Google Patents.
EP0275905A2
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A self-aligned field effect transistor including method
Assignee: International Standard Electric Corp
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Filing: 1988-01-13
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Granted: —
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Expires: 2008-01-13
Abstract
Abstract A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET's have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtain from a self-aligned FET.
Inventors
- 👤 Edward Lawrence Griffin
- 👤 Robert Allan Sadler
- 👤 Arthur Eugène Geissberger
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 03:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; Y; Y10; Y10S; Y10S148/00; Y10S148/105; Y10S148/106
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
113 words
In a self-aligned gate FET device of the type employing a semiconductor substrate having an active channel region found on a surface with a first area of said channel being a source area and a second area of said substrate being a drain area each of said areas being highly doped with a center portion of said channel joining said areas, with said center portion being reserved for a gate electrode area, the improvement in combination, therewith, of a metal layer extending from said center portion and asymmetrically disposed with said metal layer adjacent said source area on one side and separated a given distance from said drain area on the other side.
Claim 2
Dependent Claim
113 words
In a self-aligned gate FET device of the type employing a semiconductor substrate having an active channel region found on a surface with a first area of said channel being a source area and a second area of said substrate being a drain area each of said areas being highly doped with a center portion of said channel joining said areas, with said center portion being reserved for a gate electrode area, the improvement in combination, therewith, of a metal layer extending from said center portion and asymmetrically disposed with said metal layer adjacent said source area on one side and separated a given distance from said drain area on the other side.
Claim 3
Dependent Claim
19 words
The self-aligned gate FET device according to Claim 1, wherein said given distance is between 0.5 to 1.0 um.
Claim 4
Dependent Claim
24 words
The self-aligned gate FET device according to Claim 1, wherein said metal layer is selected from titanium-tungsten, titanium-tungsten nitride, tungsten nitride or tungsten silicide.
Claim 5
Dependent Claim
27 words
The self-aligned FET device according to Claim 1, further including a second metal layer on top of said extending layer and being an etch mask metal material.
Claim 6
Dependent Claim
21 words
The self-aligned FET device according to Claim 4, wherein said etch mask metal material is selected from either nickel or aluminum.
Claim 7
Independent Claim
135 words
A method of making a self-aligned gate FET device comprising the steps of: forming an active channel region on the surface of a semiconductor substrate, metallizing a gate region on said channel region relatively near a central portion thereof, forming a photoresist over said gate region to define a source and a drain region on either side of said gate region, opening holes in said photoresist on each side of said gate region with said photoresist extending a greater distance into said drain region than said source region and, doping said drain and source regions via said holes to provide asymmetrical located source and drain regions as compared to said gate region, whereby said gate region has one side adjacent said source region and the other side separated a given distance from said drain region.
Claim 8
Independent Claim
135 words
A method of making a self-aligned gate FET device comprising the steps of: forming an active channel region on the surface of a semiconductor substrate, metallizing a gate region on said channel region relatively near a central portion thereof, forming a photoresist over said gate region to define a source and a drain region on either side of said gate region, opening holes in said photoresist on each side of said gate region with said photoresist extending a greater distance into said drain region than said source region and, doping said drain and source regions via said holes to provide asymmetrical located source and drain regions as compared to said gate region, whereby said gate region has one side adjacent said source region and the other side separated a given distance from said drain region.
Claim 9
Dependent Claim
16 words
The method according to Claim 6, wherein said given distance is between .5 and 1.0 um.
Claim 10
Dependent Claim
44 words
The method according to Claim 6, wherein the step of metallizing includes metallizing said surface with a metal selected from titanium-tungsten, titanium-tungsten nitride, titanium nitride or tungsten silicide and then forming a metal etch mask over said metallization to form said gate electrode area.
Claim 11
Dependent Claim
33 words
The method according to Claim 8, wherein said metal etch mask is formed by evaporation of a metal selected from aluminum or nickel and lifted off after evaporation to form said etch mask.
Claim 12
Dependent Claim
18 words
The method according to Claim 9, wherein said doping is accommodated by implanting silicon ions in said substrate.
Claim 13
Dependent Claim
11 words
The metal according to Claim 6, wherein said substrate is GaAs.
Claim 14
Dependent Claim
31 words
The method according to Claim 6, further including the step of encapsulating said wafer with a dielectric after doping said regions and then annealing said encapsulated wafer at a given temperature.
Claim 15
Dependent Claim
19 words
The method according to Claim 12 wherein said dielectric is selected from silicon oxy-nitride, silicon dioxide or silicon nitride.
Claim 16
Dependent Claim
19 words
The method according to Claim 12, wherein said given temperature is in a range between 750 to 1000° C.
Claim 17
Dependent Claim
32 words
The method according to Claim 12, further including the step of opening windows in said encapsulant after annealing and depositing ohmic contacts within said windows to contact said source and gate areas.
Claim 18
Dependent Claim
29 words
The method according to Claim 15, wherein said ohmic contacts are evaporated into said aperture by use of a metal selected from a mixture of gold, germanium and nickel.
Claim 19
Dependent Claim
31 words
The method according to Claim 15 including the step of heating said wafer after forming said contacts to a temperaure of between 350 and 500° C to alloy said ohmic contacts.
References Cited (Backward Citations)
No citation records indexed.
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