EP0273821A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit with a test function
Assignee: Fujitsu Ltd
•
Filing: 1987-12-15
•
Granted: —
•
Expires: 2007-12-15
Abstract
Abstract A semiconductor integrated circuit comprises a plurality of integrated circuit blocks (31 - 39) constituted on a wafer (30), the integrated circuit blocks being arbitrarily electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a logical operating circuit (42) for carrying out a logical operation; a pseudo-random pattern generating circuit (40) for generating a pseudo-random pattern signal; switching circuit (41) for selecting either an input signal to be processed by the logical operating circuit or the pseudo-random pattern signal in response to a test enabling signal (TE1 - TE9) which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal mode and for outputting the selected signal to the logical operating circuit; and a data compressing circuit (43) for compressing an output data signal of the logical operating circuit.
Inventors
- 👤 Koichi Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 05:01
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318335; G01R31/318385; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G01R31/318558; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
162 words
A semiconductor integrated circuit including a plurality of integrated circuit blocks (31 - 39) constituted on a wafer (30), said integrated circuit blocks being arbitrarily electrically connected to each other so as to form a system, each of said integrated circuit blocks comprising logical operating means (42) for carrying out a logical operation; pseudo-random pattern generating means (40) for generating a pseudo-random pattern signal; and data compressing means (43) for compressing an output data signal of said logical operating means, characterized in that each of said integrated circuit blocks further comprises switching means (41) for selecting either an input signal to be processed by said logical operating means or said pseudo-random pattern signal in response to a test enabling signal (TE1 - TE9) which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal operating mode, and for outputting the selected signal to said logical operating means.
Claim 2
Dependent Claim
162 words
A semiconductor integrated circuit including a plurality of integrated circuit blocks (31 - 39) constituted on a wafer (30), said integrated circuit blocks being arbitrarily electrically connected to each other so as to form a system, each of said integrated circuit blocks comprising logical operating means (42) for carrying out a logical operation; pseudo-random pattern generating means (40) for generating a pseudo-random pattern signal; and data compressing means (43) for compressing an output data signal of said logical operating means, characterized in that each of said integrated circuit blocks further comprises switching means (41) for selecting either an input signal to be processed by said logical operating means or said pseudo-random pattern signal in response to a test enabling signal (TE1 - TE9) which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal operating mode, and for outputting the selected signal to said logical operating means.
Claim 3
Dependent Claim
85 words
A semiconductor integrated circuit as claimed in claim 1, characterized in that at the time of testing said system, said switching means of each of integrated circuit blocks (31, 33) positioned at first stage of said system is controlled by the test enabling signal so as to select the pseudo-random pattern, and said switching means of each of integrated circuit blocks (35, 38) other than the blocks at the first stage is controlled by the test enabling signal so as to select the input signals.
Claim 4
Dependent Claim
55 words
A semiconductor integrated circuit as claimed in claim 2, characterized in that a compressed data signal of said data compressing means (35, 38) positioned at a final stage of said system is compared with an expected value data, and when both the data are identical to each other, the system is found to be non-defective.
Claim 5
Dependent Claim
34 words
A semiconductor integrated circuit as claimed in any of claims 1 to 3, characterized in that said plurality of integrated circuit blocks are constituted on the whole of a sheet of the wafer (30).
Claim 6
Dependent Claim
25 words
A semiconductor integrated circuit as claimed in any of claims 1 to 4, characterized in that said logical operating means (42) is a butterfly processor.
Claim 7
Dependent Claim
24 words
A semiconductor integrated circuit as claimed in any of claims 1 to 5, characterized in that said system is a fast Fourier transform processor.
Claim 8
Dependent Claim
33 words
A semiconductor integrated circuit as claimed in any of claims 1 to 6, characterized in that said pseudo-random pattern generating means is a linear feedback shift register producing a cyclic redundancy check signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.