EP0272732A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Eeprom memory cell with a single level of polysilicon writable and cancellable bit by bit
Assignee: STMicroelectronics SRL
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Filing: 1987-12-02
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Granted: —
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Expires: 2007-12-02
Abstract
Abstract The cell is formed of a selection transistor (1), a detection transistor (2) and a tunnel condenser (3). The detection transistor (2) has its own control gate (20) formed with an n⁺ diffusion (15) which is closed and isolated from those of the other cells of the same memory.
Inventors
- 👤 Paolo Giuseppe Cappelletti
- 👤 Giuseppe Corda
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:00
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
93 words
EEPROM memory cell comprising a selection transistor (1), a detection transistor (2) with floating gate (13) and control gate (20) and a tunnel condenser (3) with a thin oxide zone (8) formed using a single layer of polysilicon (9) for the gate (10) of the selection transistor (1), the floating gate (13) of the detection transistor (2) and the tunnel condenser (3) and an n⁺ diffusion (15) for the control gate (20) characterized in that said n⁺ diffusion (15) is closed and isolated from that of the other cells of the same memory.
Claim 2
Dependent Claim
93 words
EEPROM memory cell comprising a selection transistor (1), a detection transistor (2) with floating gate (13) and control gate (20) and a tunnel condenser (3) with a thin oxide zone (8) formed using a single layer of polysilicon (9) for the gate (10) of the selection transistor (1), the floating gate (13) of the detection transistor (2) and the tunnel condenser (3) and an n⁺ diffusion (15) for the control gate (20) characterized in that said n⁺ diffusion (15) is closed and isolated from that of the other cells of the same memory.
Claim 3
Dependent Claim
118 words
Memory cell in accordance with claim 1 characterized in that said single layer of polysilicon (9) comprises a first straight strip part (10) forming the gate of the selection transistor (1) and a second part (11) formed of a first branch (12) superimposed on the thin oxide zone (8) on a first active area (6) of a semiconductor substrate (4) to form the tunnel condenser (3), a second branch (13) superimposed on said first active area (6) to form the floating gate of the detection transistor (2) and a space (14) superimposed on said n⁺ diffusion (15) on a second active area (5) of said substrate (4) to form the control gate (20) of the detection transistor (2).
Claim 4
Dependent Claim
27 words
Memory cell in accordance with claim 2 characterized in that said thin oxide zone (8) is formed of a branch (19) of said first active area (6).
References Cited (Backward Citations)
No citation records indexed.
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