EP0272051A2
Expired / Lapsed
EP
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Reduced area butting contact structure
Assignee: Advanced Micro Devices Inc
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Filing: 1987-12-10
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Granted: —
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Expires: 2007-12-10
Abstract
Abstract A reduced area butting contact structure (10ʹ) is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26ʹ). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and si continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.
Inventors
- 👤 Craig S. Sander
- 👤 Richard K. Klein
- 👤 Tat C. Choi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 11:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10W20/056; H10W20/062
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
195 words
A reduced area butting contact structure for an integrated circuit for interconnecting by means of a conductive plug a doped region of a semiconductor material with at least one polysilicon segment selected from the group consisting of a first-layer polysilicon segment and at least one upper-layer polysilicon segment, wherein (a) said first-layer polysilicon segment is separated from said doped region by a thin oxide layer and said at least one upper-layer polysilicon segment is positioned between and bordered above and below by upper layers of insulating material; (b) said conductive plug comprises a conductive material confined in and substantially filling a contact hole; (c) said contact hole is positioned over a portion of said doped region and portions of said first-layer polysilicon segment and a portion of said at least one upper-layer polysilicon segment which are contacted; and (d) said contact hole extends from the surface of the uppermost said upper layer of insulating material through said portions of said at least one upper-layer polysilicon segment which are contacted and said upper layers of insulating material down to and terminating on said portion of said first-layer polysilicon segment and said portion of said doped region.
Claim 2
Dependent Claim
195 words
A reduced area butting contact structure for an integrated circuit for interconnecting by means of a conductive plug a doped region of a semiconductor material with at least one polysilicon segment selected from the group consisting of a first-layer polysilicon segment and at least one upper-layer polysilicon segment, wherein (a) said first-layer polysilicon segment is separated from said doped region by a thin oxide layer and said at least one upper-layer polysilicon segment is positioned between and bordered above and below by upper layers of insulating material; (b) said conductive plug comprises a conductive material confined in and substantially filling a contact hole; (c) said contact hole is positioned over a portion of said doped region and portions of said first-layer polysilicon segment and a portion of said at least one upper-layer polysilicon segment which are contacted; and (d) said contact hole extends from the surface of the uppermost said upper layer of insulating material through said portions of said at least one upper-layer polysilicon segment which are contacted and said upper layers of insulating material down to and terminating on said portion of said first-layer polysilicon segment and said portion of said doped region.
Claim 3
Dependent Claim
26 words
The contact structure of Claim 1 wherein said doped region is interconnected with both said first-layer polysilicon segment and said at least one upper-layer polysilicon segment.
Claim 4
Dependent Claim
104 words
A reduced area butting contact structure for an integrated circuit for interconnecting a doped region of a semiconductor material with a first-layer-polysilicon segment thereover by means of a conductive plug, said first-layer polysilicon segment being separated from said doped region by a thin oxide layer and being covered by an upper layer of insulating material, wherein said conductive plug comprises a conductive material confined in and substantially filling a contact hole, and wherein said contact hole extends from the surface of said upper insulating layer down to and terminating on a portion of said first polysilicon segment and a portion of said doped region.
Claim 5
Dependent Claim
104 words
A reduced area butting contact structure for an integrated circuit for interconnecting a doped region of a semiconductor material with a first-layer-polysilicon segment thereover by means of a conductive plug, said first-layer polysilicon segment being separated from said doped region by a thin oxide layer and being covered by an upper layer of insulating material, wherein said conductive plug comprises a conductive material confined in and substantially filling a contact hole, and wherein said contact hole extends from the surface of said upper insulating layer down to and terminating on a portion of said first polysilicon segment and a portion of said doped region.
Claim 6
Dependent Claim
27 words
A contact structure according to any one of the claims 1-3 wherein said thin oxide layer is used as a gate dielectric elsewhere in said integrated circuit.
Claim 7
Dependent Claim
147 words
A reduced area butting contact structure for an integrated circuit for interconnecting a doped region of a semiconductor material with at least one upper-layer polysilicon segment by means of a conductive plug, wherein (a) said at least one upper-layer polysilicon segment is positioned between and bordered above and below by layers of insulating material; (b) said conductive plug comprises a conductive material confined in and substantially filling a contact hole; (c) said contact hole is positioned over a portion of said doped region and portions of any of said at least one upper-layer polysilicon segment which are contacted; and (d) said contact hole extends from the surface of the uppermost said layer of insulating material through portions of said a least one upper-layer polysilicon segment which are contacted and through said upper layers of insulating material down to and terminating on said portion of said doped region.
Claim 8
Dependent Claim
147 words
A reduced area butting contact structure for an integrated circuit for interconnecting a doped region of a semiconductor material with at least one upper-layer polysilicon segment by means of a conductive plug, wherein (a) said at least one upper-layer polysilicon segment is positioned between and bordered above and below by layers of insulating material; (b) said conductive plug comprises a conductive material confined in and substantially filling a contact hole; (c) said contact hole is positioned over a portion of said doped region and portions of any of said at least one upper-layer polysilicon segment which are contacted; and (d) said contact hole extends from the surface of the uppermost said layer of insulating material through portions of said a least one upper-layer polysilicon segment which are contacted and through said upper layers of insulating material down to and terminating on said portion of said doped region.
Claim 9
Dependent Claim
23 words
A contact structure according to any one of the preceding claims wherein said plug comprises a conductive material which can be conformally deposited.
Claim 10
Dependent Claim
15 words
The contact structure of claim 6 wherein said conductive material comprises tungsten or doped polysilicon.
Claim 11
Dependent Claim
199 words
In a four-transistor static RAM cell, a reduced area butting contact structure for interconnecting a doped region of a semiconductor material with a first-layer polysilicon segment and at least one upper-layer polysilicon segment by means of a conductive plus wherein (a) said first-layer polysilicon segment is separated from said doped region by a thin oxide layer used as a gate dielectric elsewhere in said cell and said at least one upper-layer polysilicon segment is positioned between and bordered above and below by upper layers of insulating material; (b) said conductive plug consists essentially of a tungsten or doped polysilicon confined in and substantially filling a contact hole; (c) said contact hole is positioned over a portion of said doped region and portions of said first-layer polysilicon segment and portions of said said at least one upper-layer polysilicon segment which are contacted; and (d) said contact hole extends from the surface of the uppermost said upper layer of insulating material through said portions of said at least one upper-layer polysilicon segment which are contacted and said upper layers of insulating material down to and terminating on said portion of said first-layer polysilicon segment and said portion of said doped region.
Claim 12
Dependent Claim
199 words
In a four-transistor static RAM cell, a reduced area butting contact structure for interconnecting a doped region of a semiconductor material with a first-layer polysilicon segment and at least one upper-layer polysilicon segment by means of a conductive plus wherein (a) said first-layer polysilicon segment is separated from said doped region by a thin oxide layer used as a gate dielectric elsewhere in said cell and said at least one upper-layer polysilicon segment is positioned between and bordered above and below by upper layers of insulating material; (b) said conductive plug consists essentially of a tungsten or doped polysilicon confined in and substantially filling a contact hole; (c) said contact hole is positioned over a portion of said doped region and portions of said first-layer polysilicon segment and portions of said said at least one upper-layer polysilicon segment which are contacted; and (d) said contact hole extends from the surface of the uppermost said upper layer of insulating material through said portions of said at least one upper-layer polysilicon segment which are contacted and said upper layers of insulating material down to and terminating on said portion of said first-layer polysilicon segment and said portion of said doped region.
Claim 13
Dependent Claim
25 words
A contact structure according to any one of the preceding claims wherein said doped region is doped N⁺ and said polysilicon plug is doped N⁺.
Claim 14
Dependent Claim
24 words
A contact structure according to any one of claims 1-8 wherein said doped region is doped P⁺ and said polysilicon plug is doped P⁺.
Claim 15
Dependent Claim
31 words
A contact structure according to any one of the preceding claims wherein at least one of said upper-layer polysilicon segments is doped so as to form a high resistance load device.
Claim 16
Dependent Claim
30 words
A contact structure according to any one of the claims 1-10 wherein at least one of said upper-layer polysilicon segments is doped so as to form a low resistance interconnect.
Claim 17
Dependent Claim
26 words
A contact structure according to any one of the preceding claims further provided with an insulating plug cover to prevent shorting to an overlying metal interconnect.
Claim 18
Dependent Claim
18 words
A contact structure according to claim 13 wherein said insulating plug cover comprises silicon dioxide or silicon nitride.
Claim 19
Dependent Claim
116 words
A process for providing a reduced area butting contact structure in an integrated circuit, a portion of said integrated circuit including a doped region of a semiconductor material and at least one upper-layer polysilicon segment, and with said at least one upper-layer polysilicon segment positioned between and bordered above and below by upper layers of insulating material, comprising the steps of: (a) patterning a contact hole geometry and etching through said upper layers of insulating material and through said at least one upper-layer polysilicon segment down to and terminating on said doped region to form said contact hole; (b) forming in said contact hole a plug of conductive material which substantially fills and is contained therein.
Claim 20
Dependent Claim
116 words
A process for providing a reduced area butting contact structure in an integrated circuit, a portion of said integrated circuit including a doped region of a semiconductor material and at least one upper-layer polysilicon segment, and with said at least one upper-layer polysilicon segment positioned between and bordered above and below by upper layers of insulating material, comprising the steps of: (a) patterning a contact hole geometry and etching through said upper layers of insulating material and through said at least one upper-layer polysilicon segment down to and terminating on said doped region to form said contact hole; (b) forming in said contact hole a plug of conductive material which substantially fills and is contained therein.
Claim 21
Dependent Claim
58 words
A process of claim 15 wherein said portion of said integrated circuit further includes a first-layer polysilicon segment connected to the gate of a MOS transistor, a portion of which is separated from said doped region by a gate oxide, and wherein the etching of said contact hole also terminates on a portion of said first-layer polysilicon segment.
Claim 22
Dependent Claim
142 words
A process for providing a reduced area butting contact structure in an integrated circuit, a portion of said integrated circuit including a doped region of a semiconductor material, a first-layer polysilicon segment connected to the gate of a MOS transistor, a portion of which is separated from said doped region by a gate oxide, and at least one upper-layer polysilicon segment positioned between and bordered above and below by upper layers of insulating material, comprising the steps of: (a) patterning a contact hole geometry and etching in a two-step process through said upper layers of insulating material and through said at least one upper layer polysilicon segment down to and terminating on said doped region and said first-layer polysilicon to form said contact hole; (b) forming in said contact hole a plug of conductive material which substantially fills and is contained therein.
Claim 23
Dependent Claim
142 words
A process for providing a reduced area butting contact structure in an integrated circuit, a portion of said integrated circuit including a doped region of a semiconductor material, a first-layer polysilicon segment connected to the gate of a MOS transistor, a portion of which is separated from said doped region by a gate oxide, and at least one upper-layer polysilicon segment positioned between and bordered above and below by upper layers of insulating material, comprising the steps of: (a) patterning a contact hole geometry and etching in a two-step process through said upper layers of insulating material and through said at least one upper layer polysilicon segment down to and terminating on said doped region and said first-layer polysilicon to form said contact hole; (b) forming in said contact hole a plug of conductive material which substantially fills and is contained therein.
Claim 24
Dependent Claim
29 words
A process according to any one of the claims 15-17 wherein said doped region of semiconductor material comprises silicon and said upper layers of insulating material comprise silicon dioxide.
Claim 25
Dependent Claim
80 words
The process of claim 18 wherein said two-step etching process comprises: (a) a first non-selective etch step comprising an anisotropic etch, non-specific to said upper-layer polysilicon segments and said upper layers of silicon dioxide, for etching through said upper-layer polysilicon segments and said upper layers of silicon dioxide; and (b) a second selective etch step comprising an anisotropic etch selective to silicon and polysilicon, for etching through any remaining portion of the lower-most of said upper layers of silicon dioxide.
Claim 26
Dependent Claim
47 words
A process of claim 19 wherein the conversation from said first non-selective etch step to said second selective etch step is performed upon completion of the etch through the lower-most of said upper-layer polysilicon segments and before reaching the doped silicon region or said first-layer polysilicon segment.
Claim 27
Dependent Claim
224 words
A process for providing a reduced area butting contact structure in a four-transistor static RAM memory cell including a doped region of silicon, a first-layer polysilicon segment connected to the gate of a MOS transistor, a portion of which is separated from said doped region by a gate oxide, and at least one upper-layer polysilicon segment positioned between and bordered above and below by upper layers of silicon dioxide comprising the steps of: (a) patterning a contact hole geometry and etching in a two-step process through said upper layers of silicon dioxide and through said at least one upper-layer polysilicon segment down to and terminating on said doped region and said first-layer polysilicon to form said contact hole, said two-step process comprising (1) a first non-selective etch step comprising anisotropic etch, non-specific to said upper-layer polysilicon segments and said upper layers of silicon dioxide, for etching through said upper-layer polysilicon segments and said upper layers of silicon dioxide, and (2) a second selective etch step comprising an anisotropic etch selective to silicon and polysilicon, for etching through any remaining portion of the lower-most of said upper layers of silicon dioxide; and (b) forming in said contact hole a plug consisting of tungsten or doped polysilicon which substantially fills and is contained therein, said doped polysilicon having the same conductivity type as said doped region.
Claim 28
Dependent Claim
224 words
A process for providing a reduced area butting contact structure in a four-transistor static RAM memory cell including a doped region of silicon, a first-layer polysilicon segment connected to the gate of a MOS transistor, a portion of which is separated from said doped region by a gate oxide, and at least one upper-layer polysilicon segment positioned between and bordered above and below by upper layers of silicon dioxide comprising the steps of: (a) patterning a contact hole geometry and etching in a two-step process through said upper layers of silicon dioxide and through said at least one upper-layer polysilicon segment down to and terminating on said doped region and said first-layer polysilicon to form said contact hole, said two-step process comprising (1) a first non-selective etch step comprising anisotropic etch, non-specific to said upper-layer polysilicon segments and said upper layers of silicon dioxide, for etching through said upper-layer polysilicon segments and said upper layers of silicon dioxide, and (2) a second selective etch step comprising an anisotropic etch selective to silicon and polysilicon, for etching through any remaining portion of the lower-most of said upper layers of silicon dioxide; and (b) forming in said contact hole a plug consisting of tungsten or doped polysilicon which substantially fills and is contained therein, said doped polysilicon having the same conductivity type as said doped region.
Claim 29
Dependent Claim
46 words
The process of claim 21 wherein the conversion from said first non-selective etch step to said second selective etch step is performed upon completion of the etch through the lower-most of said upper-layer polysilicon segments and before reaching said doped region or said first-layer polysilicon segment.
Claim 30
Dependent Claim
34 words
A process according to any one of the claims 15-22 wherein said first non-selective etch step etches said silicon dioxides at a rate ranging from about 0.75 to 1.5 times that of said polysilicon.
Claim 31
Dependent Claim
36 words
A process according to any one of the claims 15-23 wherein said second selective etch step etches said silicon dioxide at a rate of at least about 10 times that of said silicon and said polysilicon.
Claim 32
Dependent Claim
22 words
A process according to any one of the claims 15-24 wherein said etch comprises reactive ion etching, using CHF₃ and O₂ chemistry.
Claim 33
Dependent Claim
34 words
A process according to any one of the claims 15-25 wherein said contact hole is formed at the same time that contact holes for interconnecting metal to doped regions or to polysilicon are formed.
Claim 34
Dependent Claim
25 words
A process according to any one of the claims 15-26 additionally comprising forming an insulating plug cover between said plug and an overlying metal interconnect.
Claim 35
Dependent Claim
21 words
A process according to any one of the claims 15-27 wherein said insulating plug cover comprises silicon dioxide or silicon nitride.
References Cited (Backward Citations)
No citation records indexed.
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