EP0271932A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
EEPROM memory cell with two levels of polysilicon and a tunnel oxide zone
Assignee: STMicroelectronics SRL
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Filing: 1987-10-23
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Granted: —
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Expires: 2007-10-23
Abstract
Abstract The cell comprises a selection transistor (51), a pickup transistor (52), a thin oxide zone (56), a floating gate (58) superimposed on said thin oxide zone (56) and made with a first layer of polysilicon (57) in a single piece with a first gate (59) of the pickup transistor (52), and a control gate (61) superimposed on said first gate (59) of the pickup transistor (52) and made with a second polysilicon layer (61). The latter also forms the selection transistor gate (51) in a single piece.
Inventors
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 05:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10B; H10B69/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
93 words
EEPROM memory cell comprising a selection transistor (51), a pickup transistor (52), a thin oxide zone (56), a floating gate (58) superimposed on said thin oxide zone (56) and made with a first polysilicon layer (57) in a single piece with a first gate (59) of the pickup transistor (52) and a control gate (61) superimposed on said first gate (59) of the pickup transistor (52) and made with a second polysilicon layer (61) characterized in that said second polysilicon layer (61) also forms the selection transistor gate (51) in a single piece.
Claim 2
Dependent Claim
93 words
EEPROM memory cell comprising a selection transistor (51), a pickup transistor (52), a thin oxide zone (56), a floating gate (58) superimposed on said thin oxide zone (56) and made with a first polysilicon layer (57) in a single piece with a first gate (59) of the pickup transistor (52) and a control gate (61) superimposed on said first gate (59) of the pickup transistor (52) and made with a second polysilicon layer (61) characterized in that said second polysilicon layer (61) also forms the selection transistor gate (51) in a single piece.
Claim 3
Dependent Claim
80 words
Memory cell in accordance with claim 1 characterized in that said first polysilicon layer (57) is formed of an axial branch shifted laterally (58) defining said floating gate (58) and a transverse branch (59) defining said first gate (59) of the pickup transistor (52) and having a central cavity (60) while said second polysilicon layer (61) is superimposed on said transverse branch (59) of the first polysilicon layer (57) and forms inside said cavity (60) the selection transistor gate (51).
Claim 4
Dependent Claim
32 words
Memory cell in accordance with claim 2 characterized in that it comprises a drain contact (63) shifted axially in relation to said transistors (51, 52) and beside said thin oxide zone (56).
References Cited (Backward Citations)
No citation records indexed.
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