Establishment of bit synchronization in a data transmitting/receiving system

Claim 1

A method of establishing bit synchronization required for receiving transmitted data in a data transmitting/receiving system, comprising: an edge detecting step for detecting edges of an input waveform; a bit synchronizing step for internally generating a bit synchronous code; an error detecting step for detecting errors between position of edges of said input waveform and positions of edges of said bit synchronous code; an error averaging step for averaging the errors obtained in said error detecting step; and a sampling step for shifting said bit synchronous code by an amount corresponding to the average error obtained in said error averaging step, thereby determining sampling points and generating a sampling signal.

Claim 2

A method of establishing bit synchronization required for receiving transmitted data in a data transmitting/receiving system, comprising: an edge detecting step for detecting edges of an input waveform; a bit synchronizing step for internally generating a bit synchronous code; an error detecting step for detecting errors between position of edges of said input waveform and positions of edges of said bit synchronous code; an error averaging step for averaging the errors obtained in said error detecting step; and a sampling step for shifting said bit synchronous code by an amount corresponding to the average error obtained in said error averaging step, thereby determining sampling points and generating a sampling signal.

Claim 3

A method of establishing bit synchronization required for receiving transmitted data in a data transmitting/receiving system, comprising: an initializing step for initializing all conditions; an edge detecting step for detecting edges of an input waveform; a counting step for counting the number of edges detected in said edge detecting step and repeating said detecting step until said number of edges becomes a predetermined value; a frequency synchronizing step for examining a position of each edge detected in said edge detecting step to detect a bit synchronous code and repeating said edge detecting step until the bit synchronous code is detected; a bit synchronizing step for internally generating a bit synchronous code; an error detecting step for detecting errors between positions of edges of the input waveform and positions of edges of said bit synchronous code; an error averaging step for averaging said errors ob­tained in said error detecting step; and a sampling step for shifting said bit synchronous code by an amount corresponding to the average error obtained in said error averaging step, thereby determining sampling points and generating a sampling signal.

Claim 4

A method of establishing bit synchronization required for receiving transmitted data in a data transmitting/receiving system, comprising: an initializing step for initializing all conditions; an edge detecting step for detecting edges of an input waveform; a counting step for counting the number of edges detected in said edge detecting step and repeating said detecting step until said number of edges becomes a predetermined value; a frequency synchronizing step for examining a position of each edge detected in said edge detecting step to detect a bit synchronous code and repeating said edge detecting step until the bit synchronous code is detected; a bit synchronizing step for internally generating a bit synchronous code; an error detecting step for detecting errors between positions of edges of the input waveform and positions of edges of said bit synchronous code; an error averaging step for averaging said errors ob­tained in said error detecting step; and a sampling step for shifting said bit synchronous code by an amount corresponding to the average error obtained in said error averaging step, thereby determining sampling points and generating a sampling signal.

Claim 6

A method of establishing bit synchronization required for receiving transmitted data in a data transmitting/receiving system, comprising: an initializing step for initializing all conditions; an edge detecting step for detecting edges of an input waveform; a bit synchronizing step for internally generating a bit synchronous code corresponding to a number of edges of said input waveform; an error detecting step for detecting errors between positions of the edges of said input waveform and positions of edges of said bit synchronous code; an error checking step for examining if each of the errors obtained in said error detecting step is within a predetermined allowable range, and if any one of the errors is out of the range, returning to said initializing step; an error accumulating step for accumulating said errors if each of the errors is within the allowable range in said error checking step; a number checking step for counting the number of the edges detected in said edge detecting step and repeating said edge detecting step, said bit synchronizing step, said error detecting step, said error checking step and said error accu­mulating step until said number becomes a predetermined value; an error averaging step for taking an average of the errors obtained in said error accumulating step; and a sampling step for shifting said bit synchronous code obtained in said bit synchronizing step by an amount corres­ ponding to the average error obtained in said error averaging step, thereby determining sampling points and generating a sampling signal.

Claim 7

A method of establishing bit synchronization required for receiving transmitted data in a data transmitting/receiving system, comprising: an initializing step for initializing all conditions; an edge detecting step for detecting edges of an input waveform; a bit synchronizing step for internally generating a bit synchronous code corresponding to a number of edges of said input waveform; an error detecting step for detecting errors between positions of the edges of said input waveform and positions of edges of said bit synchronous code; an error checking step for examining if each of the errors obtained in said error detecting step is within a predetermined allowable range, and if any one of the errors is out of the range, returning to said initializing step; an error accumulating step for accumulating said errors if each of the errors is within the allowable range in said error checking step; a number checking step for counting the number of the edges detected in said edge detecting step and repeating said edge detecting step, said bit synchronizing step, said error detecting step, said error checking step and said error accu­mulating step until said number becomes a predetermined value; an error averaging step for taking an average of the errors obtained in said error accumulating step; and a sampling step for shifting said bit synchronous code obtained in said bit synchronizing step by an amount corres­ ponding to the average error obtained in said error averaging step, thereby determining sampling points and generating a sampling signal.

Claim 8

An apparatus for establishing bit synchronization in data transmitting/receiving system, comprising: a clock circuit for generating clock signals; a counter circuit for counting time by use of said clock signals; an edge detecting circuit for detecting an edge of an input waveform and generating an edge detection signal; a latch circuit for latching the counter value of said counter circuit in response to said edge detection signal; a memory circuit for storing said counter value; a transfer circuit for transferring said counter value from said latch circuit to said memory circuit in response to said edge detection signal; a calculator circuit for detecting a pattern of bit synchronization, taking an average error of internal reference edges and determining a data sampling point from the counter value in said memory circuit; and a comparator circuit for comparing said data sampling point obtained in said calculator circuit with the counter value of said counter circuit, and generating, if they are identified with each other, a sampling signal, whereby bit synchronization is established.

Claim 9

An apparatus for establishing bit synchronization in data transmitting/receiving system, comprising: a clock circuit for generating clock signals; a counter circuit for counting time by use of said clock signals; an edge detecting circuit for detecting an edge of an input waveform and generating an edge detection signal; a latch circuit for latching the counter value of said counter circuit in response to said edge detection signal; a memory circuit for storing said counter value; a transfer circuit for transferring said counter value from said latch circuit to said memory circuit in response to said edge detection signal; a calculator circuit for detecting a pattern of bit synchronization, taking an average error of internal reference edges and determining a data sampling point from the counter value in said memory circuit; and a comparator circuit for comparing said data sampling point obtained in said calculator circuit with the counter value of said counter circuit, and generating, if they are identified with each other, a sampling signal, whereby bit synchronization is established.

Claim 11

An apparatus for establishing bit synchronization in a data transmitting/receiving system, comprising: a clock circuit for generating clock signals; a counter circuit for counting time by use of said clock signals; an edge detecting circuit for detecting an edge of an input waveform and generating an edge detection signal; a latch circuit for latching the counter value of said counter circuit in response to said edge detection signal; a calculator circuit for generating an ideal bit synchro­nous pattern, calculating an error between said ideal bit syn­chronous pattern and the counter value of the edge of said input waveform, taking an average of the errors at a predeter­mined number of edges and correcting said ideal bit synchro­nous pattern by said average error, so as to determining a sampling point; a comparator circuit for comparing the data sampling point obtained in said calculator circuit with the counter value of said counter circuit, and generating, if they are identified with each other, a sampling signal for sampling the input signal, whereby bit synchronization is established.

Claim 12

An apparatus for establishing bit synchronization in a data transmitting/receiving system, comprising: a clock circuit for generating clock signals; a counter circuit for counting time by use of said clock signals; an edge detecting circuit for detecting an edge of an input waveform and generating an edge detection signal; a latch circuit for latching the counter value of said counter circuit in response to said edge detection signal; a calculator circuit for generating an ideal bit synchro­nous pattern, calculating an error between said ideal bit syn­chronous pattern and the counter value of the edge of said input waveform, taking an average of the errors at a predeter­mined number of edges and correcting said ideal bit synchro­nous pattern by said average error, so as to determining a sampling point; a comparator circuit for comparing the data sampling point obtained in said calculator circuit with the counter value of said counter circuit, and generating, if they are identified with each other, a sampling signal for sampling the input signal, whereby bit synchronization is established.