EP0271187A2
Expired / Lapsed
EP
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Split instruction and operand cache management
Assignee: Fujitsu IT Holdings Inc
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Filing: 1987-10-05
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Granted: —
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Expires: 2007-10-05
Abstract
Abstract A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic managment of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.
Inventors
- 👤 Gary A. Woffinden
- 👤 Robert A. Ertl
- 👤 Jeffrey A. Thomas
- 👤 Theodore S. Robinson
- 👤 James P. Millar
- 👤 Christopher D. Finan
- 👤 Joseph A. Petolino, Jr.
- 👤 Ajay K. Shah
- 👤 Shen H. Wang
- 👤 Mark W. Semmelmeyer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 06:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
85 words
Apparatus in a data processing system for managing the transfer of data with respect to first and second cache memories, each data having a corresponding system memory address, said apparatus comprising: a) first means for determining whether data having a predetermined system address is present within both said first and second cache memories; and b) means, responsive to said first determining means, for transferring data having said predetermined system memory address to said first cache memory or to both said first and second cache memories.
Claim 2
Dependent Claim
85 words
Apparatus in a data processing system for managing the transfer of data with respect to first and second cache memories, each data having a corresponding system memory address, said apparatus comprising: a) first means for determining whether data having a predetermined system address is present within both said first and second cache memories; and b) means, responsive to said first determining means, for transferring data having said predetermined system memory address to said first cache memory or to both said first and second cache memories.
Claim 3
Dependent Claim
74 words
The apparatus of Claim 1 comprising: a) second means for determining whether the corresponding system memory address of data transferred to either said first or second cache memory is the same as that of data present in either said second or first cache memory, respectively; and b) means, responsive to said second determining means, for associating control data with respective data present in said first and second cache memories having corresponding system memory addresses.
Claim 4
Dependent Claim
29 words
The apparatus of Claim 2 wherein said first determining means is responsive to the control data associated with the respective data present in said first and second cache memories.
Claim 5
Dependent Claim
49 words
The apparatus of Claim 3 comprising: a) primary means for storing the corresponding system memory addresses of the respective data of said first and second cache memories; and b) secondary means for storing the corresponding system memory addresses of the respective data of said first and second cache memories.
Claim 6
Dependent Claim
35 words
The apparatus of Claim 4 wherein said second determining means includes means for comparing the corresponding system memory address of data being transferred with the respective corresponding system memory addresses stored by said secondary means.
Claim 7
Dependent Claim
208 words
Apparatus in a data processing system for managing the transfer of data within and with respect to a central processing unit of said system, each data transferred having a corresponding system memory address, said apparatus comprising: a) a first cache memory provided within said central processing unit, said first cache memory providing for the storage of data; b) a second cache memory provided within said central processing unit, said second cache memory providing for the storage of data; c) means for selectably transferring data to either said first or said second cache memory, or both; d) means for determining whether data having a predetermined system memory address is present in either said second or said first cache memory, respectively, and for providing a result status corresponding thereto; e) means, responsive to said determining means, for associating said result status with the respective data having said predetermined system memory address; and f) means for detecting whether the system memory address of data being transferred to said first or second cache memory is the same as that of data already present in both said first and second buffer memories and for selecting said transferring means so that the transfer of data is to both said first and second cache memories.
Claim 8
Dependent Claim
208 words
Apparatus in a data processing system for managing the transfer of data within and with respect to a central processing unit of said system, each data transferred having a corresponding system memory address, said apparatus comprising: a) a first cache memory provided within said central processing unit, said first cache memory providing for the storage of data; b) a second cache memory provided within said central processing unit, said second cache memory providing for the storage of data; c) means for selectably transferring data to either said first or said second cache memory, or both; d) means for determining whether data having a predetermined system memory address is present in either said second or said first cache memory, respectively, and for providing a result status corresponding thereto; e) means, responsive to said determining means, for associating said result status with the respective data having said predetermined system memory address; and f) means for detecting whether the system memory address of data being transferred to said first or second cache memory is the same as that of data already present in both said first and second buffer memories and for selecting said transferring means so that the transfer of data is to both said first and second cache memories.
Claim 9
Dependent Claim
38 words
The apparatus of Claim 6 wherein said first and second cache memories respectively comprise first and second primary tag buffers and first and second data buffers providing respective storage locations for data and the corresponding system memory addresses.
Claim 10
Dependent Claim
32 words
The apparatus of Claim 7 wherein said apparatus further comprises a secondary tag buffer for maintaining respective copies of the system memory addresses stored in said first and second primary tag buffers.
Claim 11
Dependent Claim
384 words
In a data processing system including a central processing unit, a system controller and a mainstore memory unit, wherein data lines, each having a predetermined line address, are transferred thereinbetween, wherein said central processing unit includes a cache memory having an instruction buffer, an operand buffer and a first tag buffer that provides respective storage slots for the storage of a first plurality of line addresses and corresponding control data, wherein said system controller includes a second tag buffer for the storage of a second plurality of line addresses and corresponding control data, wherein an improvement in said system provides for the control of transfers of data lines having the same line addresses as data lines stored in said instruction buffer or said operand buffer of said central processing unit, said improvement comprising: a) first status bit means for storing a respective buffer pair control data with each storage slot of said first tag buffer, the storage of buffer pair control data indicating whether the corresponding line data is stored in both said instruction and operand buffers of said central processing unit; b) second status bit means for storing a respective buffer pair control data with each storage slot of said second tag buffer, the storage of buffer pair control data indicating whether the corresponding line data is stored in both said instruction and operand buffers of said central processing unit; c) first control means, coupled to said second tag buffer, for determining whether a predetermined data line being transferred to either said instruction buffer or said operand buffer has the same line address as any line data present in either said operand or said instruction buffer, respectively, or both and for correspondingly updating the buffer pair control data of said second status bit means; d) second control means, coupled to said first tag buffer, for determining whether said predetermined data line transferred to either said instruction buffer or said operand buffer has the same line address as any other line data present in either said operand or said instruction buffer, respectively, or both; and e) selector means, responsive to said second control means, for selectively storing data to either said instruction buffer or said operand buffer, or both, and for correspondingly updating the buffer pair control data of said first status bit means.
Claim 12
Dependent Claim
384 words
In a data processing system including a central processing unit, a system controller and a mainstore memory unit, wherein data lines, each having a predetermined line address, are transferred thereinbetween, wherein said central processing unit includes a cache memory having an instruction buffer, an operand buffer and a first tag buffer that provides respective storage slots for the storage of a first plurality of line addresses and corresponding control data, wherein said system controller includes a second tag buffer for the storage of a second plurality of line addresses and corresponding control data, wherein an improvement in said system provides for the control of transfers of data lines having the same line addresses as data lines stored in said instruction buffer or said operand buffer of said central processing unit, said improvement comprising: a) first status bit means for storing a respective buffer pair control data with each storage slot of said first tag buffer, the storage of buffer pair control data indicating whether the corresponding line data is stored in both said instruction and operand buffers of said central processing unit; b) second status bit means for storing a respective buffer pair control data with each storage slot of said second tag buffer, the storage of buffer pair control data indicating whether the corresponding line data is stored in both said instruction and operand buffers of said central processing unit; c) first control means, coupled to said second tag buffer, for determining whether a predetermined data line being transferred to either said instruction buffer or said operand buffer has the same line address as any line data present in either said operand or said instruction buffer, respectively, or both and for correspondingly updating the buffer pair control data of said second status bit means; d) second control means, coupled to said first tag buffer, for determining whether said predetermined data line transferred to either said instruction buffer or said operand buffer has the same line address as any other line data present in either said operand or said instruction buffer, respectively, or both; and e) selector means, responsive to said second control means, for selectively storing data to either said instruction buffer or said operand buffer, or both, and for correspondingly updating the buffer pair control data of said first status bit means.
References Cited (Backward Citations)
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