Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
347 words
A semiconductor memory device comprising at least one memory cell array means (10; 10 1 to 10n) having N memory blocks; N buffer means (11 A to 11 H) respectively connected to said memory blocks: driver means (16; 19); data selection means (15; 20; 120; 120, to 120n) for selecting data transferred to and from said driver means (16; 19); a plurality of data buses (12A to 12D; 13A to 13D) connected to said data selection means (15; 20; 120; 120, to 120n); and control means (21; 21 B; 21 C) for supplying control signals to said data selection means (15; 20; 120; 120, to 120n) in each operation cycle, causing said data buses (12A to 12D; 13A to 13D) to be sequentially connected to said driver means (16; 19) via said data selection means (15; 20; 120; 120, to 120n), thereby permitting serial data to be transferred with respect to said memory cell array means (10; 10 1 to 10n) via said data buses (12A to 12D; 13A to 13D), characterized in that said buffer means (11 A to 11 H) are divided into n groups, n buffer selection means (14A to 14D) are each connected between a corresponding one of groups of said buffer means (11 A to 11H) and a corresponding one of said data buses (12A to 12D: 13A to 13D), and said control means (21; 21 B; 21 C) supplies control signals to said buffer selection means (14A to 14D), causing one of said buffer means (11A to 11 H) to be selectively connected to a corresponding one of said data buses (12A to 12D: 13A to 13D) via a corresponding one of said buffer selection means (14A to 14D), and causing said data buses (12A to 12D: 13A to 13D) to be sequentially connected to said driver means (16; 19) via said data selection means (15; 20; 120; 120 1 to 120n), thereby permitting serial data to be transferred with respect to said memory cell array means (10; 101 to 10n) via said data buses (12A to 12D; 13A to 13D).
Claim 2
Dependent Claim
347 words
A semiconductor memory device comprising at least one memory cell array means (10; 10 1 to 10n) having N memory blocks; N buffer means (11 A to 11 H) respectively connected to said memory blocks: driver means (16; 19); data selection means (15; 20; 120; 120, to 120n) for selecting data transferred to and from said driver means (16; 19); a plurality of data buses (12A to 12D; 13A to 13D) connected to said data selection means (15; 20; 120; 120, to 120n); and control means (21; 21 B; 21 C) for supplying control signals to said data selection means (15; 20; 120; 120, to 120n) in each operation cycle, causing said data buses (12A to 12D; 13A to 13D) to be sequentially connected to said driver means (16; 19) via said data selection means (15; 20; 120; 120, to 120n), thereby permitting serial data to be transferred with respect to said memory cell array means (10; 10 1 to 10n) via said data buses (12A to 12D; 13A to 13D), characterized in that said buffer means (11 A to 11 H) are divided into n groups, n buffer selection means (14A to 14D) are each connected between a corresponding one of groups of said buffer means (11 A to 11H) and a corresponding one of said data buses (12A to 12D: 13A to 13D), and said control means (21; 21 B; 21 C) supplies control signals to said buffer selection means (14A to 14D), causing one of said buffer means (11A to 11 H) to be selectively connected to a corresponding one of said data buses (12A to 12D: 13A to 13D) via a corresponding one of said buffer selection means (14A to 14D), and causing said data buses (12A to 12D: 13A to 13D) to be sequentially connected to said driver means (16; 19) via said data selection means (15; 20; 120; 120 1 to 120n), thereby permitting serial data to be transferred with respect to said memory cell array means (10; 101 to 10n) via said data buses (12A to 12D; 13A to 13D).
Claim 3
Dependent Claim
63 words
A semiconductor memory device according to claim 1. characterized in that said data selection means includes first and second data selection circuits (15 and 20) each connected to said data buses (12A to 12D: 13A to 13D). and said driver means includes first and second driver circuits (16 and 19) respectively connected to said first and second data selection circuits (15 and 20).
Claim 4
Dependent Claim
37 words
A semiconductor memory device according to claim 1. characterized in that said driver means includes first and second driver circuits (16 and 19) commonly connected to said data selection means (15: 20: 120; 120 1 to 120n).
Claim 5
Dependent Claim
30 words
A semiconductor memory device according to claim 2 or 3. characterized in that each of said data buses (12A to 12D: 13A to 13D) includes a pair of data lines.
Claim 6
Dependent Claim
29 words
A semiconductor memory device according to claim 2 or 3, characterized in that each of said data buses (12A to 12D; 13A to 13D) includes a single data line.
Claim 7
Dependent Claim
86 words
A semiconductor memory device according to claim 1, characterized in that said memory cell array means (10, to 10n) includes M memory cell arrays each having N memory blocks, and said data selection means (120, to 120n) includes M data selection circuits respectively connected to said M memory cell arrays (10, to 10n) via said data buses (110Al to 110Dl; ...; 110An to 110Dn), buffer selection means (14AI to 14Dl; ...; 14An to 14Dn), and buffer means (11 AI to 11 HI; ...; 11An to 11Hn).