EP0267974A1
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EP
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Control interface for transferring data between a data processing unit and input/output devices
Assignee: International Business Machines Corp
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Filing: 1986-11-14
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Granted: —
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Expires: 2006-11-14
Abstract
Abstract The IBM 370 Input/Output (I/O) architecture separates I/O devices very strictly from the central processing unit and its main memory. The I/O devices can access the memory only through the channel which takes care that only accesses to authorized spaces are performed. The invention provides a control interface that allows the I/O devices (9) to communicate with the memory directly. The memory space available for data transfer is provided to the I/O devices by two continuously running transfer mechanisms, one for inbound and one for outbound data transfer traffic. These mechanisms provide a series of buffers (2,3) which are controlled by pointers (6,7) indicating which buffers are full and which ones are empty. The current pointer values are exchanged between an application (4) and an I/O device by a third continuously running mechanism. Pointers changed are recognized by the application or by the I/O device control. The software can get control after a data transfer operation has been completed by using an interrupt mechanism. The interrupt mechanism can be tuned by the application by specifying threshold values and timers.
Inventors
- 👤 Karl-Heinz Dipl.-Phys. Dutke
- 👤 J. Gould
- 👤 J. Perchik
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 09:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/10; G06F13/12; G06F13/122; G06F5/00; G06F5/06
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
201 words
Control interface for transferring data between a data processing unit and at least one input/output (I/O) device (9), with an input/output (I/O) controller (8) connecting the I/O devices to the interface, comprising a first pool (2) of buffers (11a-n) for buffering data transferred from an I/O device to an application (4), a second pool (3) of buffers (12a-n) for buffering data transferred from an application to an I/O device, a control unit (1) having outbound pointer means (6) for controlling the outbound data transfer from an application to an I/O device, and inbound pointer means (7) for controlling an inbound data transfer from an I/O device to an application, means (15-19, 21-23, 33, 35) within the application and means (25, 26, 28, 29, 31, 32, 34, 45) within the I/O controller for changing the values of the pointers and for detecting these changes for deriving inbound control signals (XI, YI) controlling the inbound, and outbound control signals (XO, YO) controlling the outbound data transfers, the control signals depending on the buffer states free (empty) or full, and an interrupt control (13) which interrupts inbound and/or outbound data transfers if there are no free buffers available, or in cases of software interventions.
Claim 2
Dependent Claim
201 words
Control interface for transferring data between a data processing unit and at least one input/output (I/O) device (9), with an input/output (I/O) controller (8) connecting the I/O devices to the interface, comprising a first pool (2) of buffers (11a-n) for buffering data transferred from an I/O device to an application (4), a second pool (3) of buffers (12a-n) for buffering data transferred from an application to an I/O device, a control unit (1) having outbound pointer means (6) for controlling the outbound data transfer from an application to an I/O device, and inbound pointer means (7) for controlling an inbound data transfer from an I/O device to an application, means (15-19, 21-23, 33, 35) within the application and means (25, 26, 28, 29, 31, 32, 34, 45) within the I/O controller for changing the values of the pointers and for detecting these changes for deriving inbound control signals (XI, YI) controlling the inbound, and outbound control signals (XO, YO) controlling the outbound data transfers, the control signals depending on the buffer states free (empty) or full, and an interrupt control (13) which interrupts inbound and/or outbound data transfers if there are no free buffers available, or in cases of software interventions.
Claim 3
Dependent Claim
53 words
Control interface in accordance with Claim 1, wherein said outbound pointer means (6) and said inbound pointer means (7) each comprise an index pointer (6a, 7a) an acknowledgment pointer (6b, 7b), where the index pointers can only be changed by an application (4) and the acknowledgment pointers only by an I/O controller (8).
Claim 4
Dependent Claim
50 words
Control interface in accordance with Claims 1 and 2, wherein said changes are made by incrementing the index pointer value (INDEX) by a specific amount (V1) and the acknowledgment pointer value (ACKN) by a specific amount (V2) which can be equal to or different from the first named specific amount.
Claim 5
Dependent Claim
66 words
Control interface in accordance with one or more of the preceding claims, wherein said changes of said index pointers (6a, 7a) are performed by a mechanism (15, 18, 19, 21, 22) which is located in the application (4) and wherein the changes of said acknowledgment pointers (6b, 7b) are performed by a mechanism (26, 28, 29, 31, 32) which is located in the I/O controller (8).
Claim 6
Dependent Claim
82 words
Control interface in accordance with one or more of the preceding claims, where in said application (4) first index means (15) reflecting the value of the index pointer (6a, 7a) and first acknowledgement means (16) are provided reflecting the value of the acknowledgment pointer (6b, 7b), and where in said I/O controller (8) second index means (25) reflecting the value of the index pointer (6a, 7a) and second acknowledgement means (26) are provided reflecting the value of the acknowledgment pointer (6b, 7b).
Claim 7
Dependent Claim
45 words
Control interface in accordance with one or more of the preceding claims where in said application (4) storage means (17) are provided containing a number (MAX BUFFER) which equals the maximum number of b uffers used within the first (second) pool (2, 3) of buffers.
Claim 8
Dependent Claim
147 words
Control interface in accordance with one or more of the preceding claims, where in said application (4) arithmetic and logic means (23, 35) are provided generating said inbound/outbound control signals (XI,XO) when the following condition is satisfied: ([INDEX] - [ACKN]) < [MAX BUFFER] with [INDEX] being the value of the index pointer in said first index means (15), [ACKN] being the value of the aknowledgement pointer in said first acknowledgement means (16) and [MAX BUFFER] being the value of said maximum number of buffers in said storage means (17) and where in the I/O controller first logic means (45) are provided generating said inbound/outbound control signals (YI, YO) when the following condition is satisfied: [INDEX] > [ACKN] with [INDEX] being the value of the index pointer in said second index means (25) and [ACKN] being the value of the aknowledgement pointer in said second acknowledgement means (26).
Claim 9
Dependent Claim
117 words
Control interface in accordance with one or more of the preceding claims wherein said interrupt control (13) comprises first arithmetic means (40) for forming the difference between said aknowledgement pointer (6b, 7b) and the aknowledgement pointer value in said first acknowledgement means (16) which can be regarded as a "sleeping pointer" as being not updated due to missing data transfer operations of the I/O controller, said difference being compared by second logic means (41) with a threshold value in threshold means (42) generating an interrupt control signal (T3) if the following condition is satisfied: ([ACKN]-[SLPT])≦αµρ¨[THRESHOLD], said interrupt control signal being alternatively generated when an aknowledgement update allowed information contained in ackn update allowed means (43) is dropped.
Claim 10
Dependent Claim
58 words
Control interface in accordance with one or more of the preceding claims where in said application (4) a fifth transmission gate (36) is provided which is controlled by said interrupt control signal (T3) which, when blocked, does not allow an update of the aknowledgement pointer contained in said first acknowledgement means (16) by the aknowledgement pointer (6b, 7b).
Claim 11
Dependent Claim
61 words
Control interface in accordance with one or more of the preceding claims wherein data transfers between said application (4) and said inbound (outbound buffers) (2, 3) are controlled by a first transmission gate (20) within the application and wherein data transfers between said I/O controller (8) and said buffers are controlled by a second transmission gate (30) within the I/O controller.
Claim 12
Dependent Claim
186 words
Control interface in accordance with one or more of the preceding claims wherein for outbound data transfer operations the following steps are performed: 1. Dependent on said first outbound control signal (XO) the outbound data are transferred from a data source (14) within said application (4) to said outbound buffers (3) via said first transmission gate (20) and a first data line (O1), 2. the application increments the value [INDEX] of the index pointer in the first index means (15) by a specific amount (V1) and transfers the new value via a third transmission gate (21) and a first control line (O2) to the index pointer (6a) within the outbound pointers (6) and from there via a second control line (O3) to said second index means (25) within said I/O controller (8), 3. dependent on said second outbound control signal (YO) the outbound data are transfered from said outbound buffers via a second data line (O4) and said second transmission gate (30) to a data sink (24) within said I/O controller (8), 4. steps 1 to 3 are repeated until the outbound data transfers are completed.
Claim 13
Dependent Claim
192 words
Control interface in accordance with one or more of the preceding claims wherein for inbound data tr rations the following steps are performed: 1. Dependent on said second inbound control signal (YI) the inbound data are transfered from a data source (24) within said I/O controller (8) to said inbound buffers (2) via said second transmission gate (30) and a third data line (I1), 2. the I/O controller increments the value [ACKN] of the acknowledgement pointer in the second acknowledgement means (26) by a specific amount (V2) and transfers the new value via a fourth transmission gate (31) and a third control line (I2) to the acknowledgement pointer (7b) within the inbound pointers (7) and from there via a fourth control line (I3) and said fifth transmission gate (36) to said second acknowledgement means (16) within said application (4), 3. dependent on said second inbound control signal (YI) the inbound data are transfered from said inbound buffers via a fourth data line (I4) and said first transmission gate (20) to a data sink (14) within said application (4), 4. steps 1 to 3 are repeated until the outbound data transfers are completed.
Claim 14
Dependent Claim
46 words
Control interface in accordance with one or more of the preceding claims wherein for full duplex data transfer operations the steps of the claims 11 and 12 are performed in parallel in each of two sets of said data transfer mechanisms (of Figs. 3 and 4).
References Cited (Backward Citations)
EP0134115A2
Cited
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