Micro processor capable of being connected with coprocessor

Claim 2

A micro processor comprising an execution unit executing a program, a bus control unit coupled to said execution unit and controlling an address bus and a data bus to supply a command code to a coprocessor when said execution unit receives an instruction to be executed by said coprocessor, and a terminal connected to said executing unit and supplied with a busy signal which takes a first logic level when said coprocessor is in an arithmetic operating state and a second logic level when said coprocessor is not in the arithmetic operating state, whereby said execution unit detects the level of said busy signal after said command code is supplied to said coprocessor and controls said bus control unit to read status information of said coprocessor when the level of said busy signal is said second logic level.

Claim 3

The processor as claimed in claim 1, wherein said bus control unit supplies to said execution unit a bus cycle signal representating that said address and data buses are used to supply said command signal to said coprocessor, and said execution unit detects the level of said busy signal when said bus cycle signal disappears.

Claim 4

A combination comprising a master processor including an execution unit, an instruction decoder unit, a bus control unit, and a first terminal connected to said execution unit; a memory; a slave processor including an arithmetic unit, a command port, a status port, an operand port, and a second terminal connected to said arithmetic unit; a data bus interconnecting said master processor, said memory and said slave processor; and a signal line connected between said first and second terminals; said execution unit controlling said bus control unit to supply a command code to said command port via said data bus when said instruction decoder unit decodes an instruction to be executed by said slave processor; said arithmetic unit supplying via said signal line to said execution unit a busy signal representing that said arithmetic unit is in an arithmetic operating state responsive to said command code; and said execution unit controlling said bus control unit to read contents of said status and operand ports via said data bus after said busy signal disappears.

Claim 5

A combination comprising a master processor including an execution unit, an instruction decoder unit, a bus control unit, and a first terminal connected to said execution unit; a memory; a slave processor including an arithmetic unit, a command port, a status port, an operand port, and a second terminal connected to said arithmetic unit; a data bus interconnecting said master processor, said memory and said slave processor; and a signal line connected between said first and second terminals; said execution unit controlling said bus control unit to supply a command code to said command port via said data bus when said instruction decoder unit decodes an instruction to be executed by said slave processor; said arithmetic unit supplying via said signal line to said execution unit a busy signal representing that said arithmetic unit is in an arithmetic operating state responsive to said command code; and said execution unit controlling said bus control unit to read contents of said status and operand ports via said data bus after said busy signal disappears.

Claim 6

The combination as claimed in claim 3, further comprising an address bus interconnecting said master processor, said memory and said slave processor, said bus control unit selecting said command port, said status port and said operand port via said address bus.

Claim 7

A micro processor comprising an execution unit executing a program, a bus control unit coupled to said execution unit and supplying a command signal to a coprocessor via a data bus when said execution unit receives an instruction to be executed by said coprocessor, a first terminal connected to said execution unit and supplied with a busy signal representing that siad coprocessor is in an arithmetic operating state, and a second terminal connected to said execution unit and supplied with a status read request signal, whereby said execution unit controls said bus control unit to read an output data of said coprocessor without reading status information of said coprocessor when both of said busy signal and said status read request signal are absent and to read said status information of said coprocessor when said busy signal is absent and said status read request signal is present.

Claim 8

A micro processor comprising an execution unit executing a program, a bus control unit coupled to said execution unit and supplying a command signal to a coprocessor via a data bus when said execution unit receives an instruction to be executed by said coprocessor, a first terminal connected to said execution unit and supplied with a busy signal representing that siad coprocessor is in an arithmetic operating state, and a second terminal connected to said execution unit and supplied with a status read request signal, whereby said execution unit controls said bus control unit to read an output data of said coprocessor without reading status information of said coprocessor when both of said busy signal and said status read request signal are absent and to read said status information of said coprocessor when said busy signal is absent and said status read request signal is present.