EP0266147A2
Expired / Lapsed
EP
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A phase-lock-loop circuit for a television apparatus
Assignee: RCA Licensing Corp
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Filing: 1987-10-26
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Granted: —
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Expires: 2007-10-26
Abstract
Abstract A digital phase-lock-loop circuit (20) includes a generator (21) that produces a horizontal rate output signal (CT) at a controlled frequency and a phase detector (202) responsive to the output signal (CT) and to an incoming synchronizing signal (H s ). The phase detector (202) is coupled to the generator control port (21a) via a loop filter (33). When the phase between the output signal (CT) and the synchronizing signal (H s ) that synchronizes the phase-lock-loop circuit (20) changes as a result of, for example, head switching in a two-head VTR that supplies the synchronizing signal, a signal (PH) representative of such phase change is produced. The phase change representative signal (PH) is fed forward to the generator (21) by bypassing (through 120) the loop filter (33) of the phase-lock-loop circuit (20). The phase change representative signal (PH) produces an immediate phase shift of the output signal (CT) such that the loop filter (33) is not affected by the head switching.
Inventors
- 👤 Alvin Reuben Balaban
- 👤 Steven Alan Steckler
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:08
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
302 words
A phase-lock-loop circuit of a television apparatus, comprising: a source (60) of a synchronizing input signal (H s ) at a given phase; a controllable generator (21) responsive to said input signal for generating a periodic output signal (CT) at a frequency that is related to the frequency of said input signal and at a phase that is controlled in accordance with said given phase of said input signal; a phase detector (202) responsive to said output (CT) and input (H s ) signals for producing a signal (PH) that is indicative of a phase difference therebetween; a low-pass filter (33) responsive to said phase difference indicative signal (PH) for producing, in accordance therewith, a first signal (PERIOD) that is coupled to said generator (21) to form a feedback loop path (20) for controlling said phase of said output signal (CT) such that, when a change between said given phase of said input signal (H s ) and said phase of said output signal (CT) occurs, said first signal (PERIOD) varies to cause a corresponding change in said phase of said output signal (CT) in a manner that reduces the phase difference between said input and output signals for synchronizing said output to said input signal; characterized by means (120) coupled to said feedback loop path (20) between said phase detector (202) and said low-pass filter (33) for generating, in accordance with the phase difference that is contained in said phase difference indicative signal (PH), a second signal (VCRMOD) when said change is said phase difference indicative signal (PH) meets a predetermined criterion, said second signal (VCRMOD) being coupled to said generator (21) to produce at least a portion of said change in said phase of said output signal (CT) that synchronizes said output (CT) to said input (H s ) signal.
Claim 2
Dependent Claim
302 words
A phase-lock-loop circuit of a television apparatus, comprising: a source (60) of a synchronizing input signal (H s ) at a given phase; a controllable generator (21) responsive to said input signal for generating a periodic output signal (CT) at a frequency that is related to the frequency of said input signal and at a phase that is controlled in accordance with said given phase of said input signal; a phase detector (202) responsive to said output (CT) and input (H s ) signals for producing a signal (PH) that is indicative of a phase difference therebetween; a low-pass filter (33) responsive to said phase difference indicative signal (PH) for producing, in accordance therewith, a first signal (PERIOD) that is coupled to said generator (21) to form a feedback loop path (20) for controlling said phase of said output signal (CT) such that, when a change between said given phase of said input signal (H s ) and said phase of said output signal (CT) occurs, said first signal (PERIOD) varies to cause a corresponding change in said phase of said output signal (CT) in a manner that reduces the phase difference between said input and output signals for synchronizing said output to said input signal; characterized by means (120) coupled to said feedback loop path (20) between said phase detector (202) and said low-pass filter (33) for generating, in accordance with the phase difference that is contained in said phase difference indicative signal (PH), a second signal (VCRMOD) when said change is said phase difference indicative signal (PH) meets a predetermined criterion, said second signal (VCRMOD) being coupled to said generator (21) to produce at least a portion of said change in said phase of said output signal (CT) that synchronizes said output (CT) to said input (H s ) signal.
Claim 3
Dependent Claim
65 words
A circuit according to Claim 1 characterized in that said second signal (VCRMOD) is generated when a rate of said change in said phase difference indicative signal (PH) is greater than a first predetermined value such that, after said change in said phase difference indicative signal occurs, said rate of change in said phase difference indicative signal (PH) becomes smaller than a second predetermined value.
Claim 4
Dependent Claim
80 words
A circuit according to Claim 1 characterized in that when said criterion is met, said second signal generating means (120) establishes said second signal (VCRMOD) at a corresponding value that is indicative of a magnitude of the phase difference such that a magnitude of said portion of said change in said phase of said output signal that is caused by said second signal is substantially unaffected by said feedback loop path after said value of said second signal is established.
Claim 5
Dependent Claim
21 words
A circuit according to Claim 1 characterized in that said input signal (H s ) is at the horizontal deflection frequency.
Claim 6
Dependent Claim
37 words
A circuit according to Claim 4 characterized in that said second signal generating means (120) is responsive to a signal (V s ) at a vertical rate to generate said second signal (VCRMOD) only during vertical blanking.
Claim 7
Dependent Claim
52 words
A circuit according to Claim 1 characterized in that said second signal generating means (120) is responsive to said signal (PH) that is produced by said phase detector (202) for generating therefrom said second signal (VCRMOD) that is coupled to said generator (21) in a manner that bypasses said low-pass filter (33).
Claim 8
Dependent Claim
73 words
A circuit according to Claim 1 characterized by, combining means (201) responsive to said first (PERIOD) and second (VCRMOD) signals for combining said first and second signals to produce a third signal (RESET) that is coupled to said generator (21) to control said phase of said output signal (CT) such that said phase of said output signal is simultaneously affected by corresponding values of each of said first (PERIOD) and second (VCRMOD) signals.
Claim 9
Dependent Claim
64 words
A circuit according to Claim 1 characterized in that said second signal generating means (120) generates said second signal (VCRMOD) after a change in said given phase of said input signal (H s ) occurs that results in said input signal (H s ) being at a phase that is stable and that is shifted relative to said phase of said output signal (CT).
Claim 10
Dependent Claim
71 words
A circuit according to Claim 1 characterized in that said controllable generator (21) comprises sequential means for generating said output signal (CT) in accordance with a sequence of states that change in synchronism with a clock signal (CK) and wherein said second signal (VCRMOD) causes said sequence of states that corresponds with a corresponding period of said input signal (H s ) to vary in accordance with said second signal (VCRMOD).
Claim 11
Dependent Claim
27 words
A circuit according to Claim 9 characterized in that said sequential means (21) performs a function analogous to that of an oscillator of an analog phase-lock-loop circuit.
Claim 12
Dependent Claim
40 words
A circuit according to Claim 9 characterized in that when said change in said phase of said output signal (CT) that is caused by said second signal (VCRMOD), occurs, it occurs abruptly and in synchronism with said clock signal (CK).
Claim 13
Dependent Claim
55 words
A circuit according to Claim 1 characterized in that said second signal (VCRMOD) causes said change in said phase of said output signal (CT) when said predetermined criterion is detected by an amount that is related to an amount by which the phase difference is different from a steady state value of the phase difference.
Claim 14
Dependent Claim
52 words
A circuit according to Claim 1 characterized in that said first signal (PERIOD) is indicative of a length of a given period of said output signal (CT), and wherein said first signal (PERIOD) remains substantially unaffected when said change in said phase difference indicative signal (PH) occurs that meets said predetermined criterion.
Claim 15
Dependent Claim
287 words
A phase-lock-loop circuit of a television apparatus, comprising: a source (60) of a synchronizing input signal (H s ) at a frequency that is related to the deflection frequency and at a given phase; a source of a clock signal (CK); sequential means (21) responsive to said clock signal (CK) for generating a periodic output signal (CT),. said output signal containing, in a given period thereof, a sequence of states such that a change of state in said sequence occurs in synchronism with said clock signal; A phase detector (202) responsive to said output (CT) and input (H s ) signals for generating a signal (PH) that is indicative of a phase difference therebetween; a low-pass filter (33) responsive to said signal (PH) that is generated by said phase detector (202) for generating a first signal (PERIOD), that is coupled to said sequential means (21), that varies the number of said states in said sequence of said output signal(CT) in accordance with the phase difference signal (PH), such that said sequential means (21), low-pass filter (33) and phase detector (202) form a feed-back loop arrangement (20) that synchronizes said output signal (CT) to said input signal (H s ); and means (120) responsive to said signal (PH) that is generated by said phase detector (202) for generating a second signal (VCRMOD) when a change of phase in said input signal (H s ) occurs that meets a predetermined criterion, said second signal (VCRMOD) being coupled to said sequential means (21) for varying said phase of said output signal (CT), in accordance with the phase difference signal (PH), in a manner that speeds up the synchronization of said output signal (CT) to said input signal (H s ).
Claim 16
Dependent Claim
287 words
A phase-lock-loop circuit of a television apparatus, comprising: a source (60) of a synchronizing input signal (H s ) at a frequency that is related to the deflection frequency and at a given phase; a source of a clock signal (CK); sequential means (21) responsive to said clock signal (CK) for generating a periodic output signal (CT),. said output signal containing, in a given period thereof, a sequence of states such that a change of state in said sequence occurs in synchronism with said clock signal; A phase detector (202) responsive to said output (CT) and input (H s ) signals for generating a signal (PH) that is indicative of a phase difference therebetween; a low-pass filter (33) responsive to said signal (PH) that is generated by said phase detector (202) for generating a first signal (PERIOD), that is coupled to said sequential means (21), that varies the number of said states in said sequence of said output signal(CT) in accordance with the phase difference signal (PH), such that said sequential means (21), low-pass filter (33) and phase detector (202) form a feed-back loop arrangement (20) that synchronizes said output signal (CT) to said input signal (H s ); and means (120) responsive to said signal (PH) that is generated by said phase detector (202) for generating a second signal (VCRMOD) when a change of phase in said input signal (H s ) occurs that meets a predetermined criterion, said second signal (VCRMOD) being coupled to said sequential means (21) for varying said phase of said output signal (CT), in accordance with the phase difference signal (PH), in a manner that speeds up the synchronization of said output signal (CT) to said input signal (H s ).
Claim 17
Dependent Claim
49 words
A circuit according to Claim 14 characterized in that said second signal generating means (120) generates said second signal (VCRMOD) that causes the number of states in said sequence of said given period to vary by an amount that is determined in accordance with the phase difference signal (PH).
Claim 18
Dependent Claim
22 words
A circuit according to Claim 14 characterized in that said second signal (VCRMOD) reduces a transient variation in said first signal (PERIOD).
Claim 19
Dependent Claim
35 words
A circuit according to Claim 14 characterized in that variation of said phase of said output signal (CT) that is caused by said second signal (VCRMOD) occurs in a manner that bypasses said filter (33).
Claim 20
Dependent Claim
19 words
A circuit according to Claim 14 characterized in that said second signal generating means (120) comprises a microprocessor (306).
Claim 21
Dependent Claim
68 words
A circuit according to Claim 14 characterized in that said second signal generating means (120) comprises means responsive to said phase difference indicative signal (PH) for generating said second signal (VCRMOD) at a value that is in accordance with a difference between the phase difference resulting from said change in said phase of said input signal (H s ) and a steady state value of said phase difference.
Claim 22
Dependent Claim
108 words
A circuit according to Claim 14 characterized in that said second signal generating means (120) comprises means (305) responsive to said phase difference indicative signal (PH) for generating a third signal (TRUE) when a rate of change of said phase difference indicative signal (PH) is greater than a first predetermined magnitude and a fourth signal (FALSE) when said rate of change of said phase difference indicative signal (PH) is smaller than a second predetermined magnitude, and means (306) responsive to said third (TRUE) and fourth (FALSE) signals for generating said second signal (VCRMOD) when said fourth signal (FALSE) occurs after an occurrence of said third signal (TRUE) .
Claim 23
Dependent Claim
40 words
A circuit according to Claim 14 characterized in that said second signal generating means (120) comprises means (300) for generating a third signal (PH AV ) that is indicative of a running average of said phase difference indicative signal (PH).
Claim 24
Dependent Claim
55 words
A circuit according to Claim 14 characterized in that said second signal (VCRMOD) causes an abrupt shift in said phase of said output signal (CT) after said predetermined criterion is met to synchronize said output to said input signal (H s ) such that a long transient state in said first signal (PERIOD) is prevented.
Claim 25
Dependent Claim
58 words
An apparatus according to Claim 20 characterized in that variation of said phase of said output signal (CT) that is caused by said second signal (VCRMOD) causes the phase difference between said output (CT) and input (H s ) signals that occurs during a transient state to become equal immediately to a steady-state value of the phase difference.
References Cited (Backward Citations)
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