Debugging microprocessor

Claim 2

A debugging processor which includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, and an interrupt control unit for notifying the instruction execution unit of an interrupt request, characterized in that it comprises a debug interrupt response control unit having a priority higher than that of the interrupt control unit and having a fixed branch destination address, the debug interrupt response control unit operating to generate to the external a debug interrupt response signal which becomes active during a period of save operation for an internal information.

Claim 3

A debugging microprocessor claimed in Claim 1 wherein the interrupt control unit receives a non-maskable interrupt and a debug interrupt independently of each other, and when the non-maskable interrupt and the debug interrupt are concurrently generated, the interrupt control unit firstly notifies the execution unit that the non-maskable interrupt has been requested, and thereafter, notifies the execution unit that the debug interrupt has been requested.

Claim 4

A debugging microprocessor claimed in Claim 2 wherein when the execution unit is notified that the non-maskable interrupt has been requested, the execution unit reads the content of a memory location storing a branch destination address for a non-maskable interrupt operation, and when the execution unit is thereafter immediately notified that the debug interrupt has been requested, the execution unit performs the save operation for a program counter and a program status word, and then, moves to the operation of the debug interrupt.

Claim 5

A microprocessor development support system coupled with a memory storing a program to be debugged and receiving a non-maskable interrupt from an external, comprising a controller coupled to the first named memory through an internal access bus and generating a break request, a second memory storing a debugging program and coupled to the internal access bus, a third memory coupled to the internal access bus so as to save a necessary information, and a debugging microprocessor selectively coupled to one of the first memory and the second memory so as to execute one of the program to be debugged and the debugging program, the debugging microprocessor receiving the non-maskable interrupt and the break request independently of each other for generating a debug interrupt response signal to the controller and the second and third memories, the debug interrupt response signal being brought into a predetermined level only for a period of a saving operation of necessary information to the third memory.

Claim 6

A microprocessor development support system coupled with a memory storing a program to be debugged and receiving a non-maskable interrupt from an external, comprising a controller coupled to the first named memory through an internal access bus and generating a break request, a second memory storing a debugging program and coupled to the internal access bus, a third memory coupled to the internal access bus so as to save a necessary information, and a debugging microprocessor selectively coupled to one of the first memory and the second memory so as to execute one of the program to be debugged and the debugging program, the debugging microprocessor receiving the non-maskable interrupt and the break request independently of each other for generating a debug interrupt response signal to the controller and the second and third memories, the debug interrupt response signal being brought into a predetermined level only for a period of a saving operation of necessary information to the third memory.

Claim 7

A system claimed in Claim 4 wherein the debugging processor includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, an interrupt control unit receiving the non-maskable interrupt and the break request for notifying the instruction execution unit of an interrupt request, and a debug interrupt response control unit having a fixed branch destination address and coupled to the execution unit and the bus control unit so as to generate the debug interrupt response signal.

Claim 8

A system claimed in Claim 5 wherein the interrupt control unit receives a non-maskable interrupt and a debug interrupt independently of each other, and when the non-­maskable interrupt and the debug interrupt are concurrently generated, the interrupt control unit firstly notifies the execution unit that the non-maskable interrupt has been requested, and thereafter, notifies the execution unit that the debug interrupt has been requested.

Claim 9

A system claimed in Claim 6 wherein when the execution unit is notified that the non-maskable interrupt has been requested, the execution unit reads the content of a memory location storing a branch destination address for a non-­maskable interrupt operation, and when the execution unit is thereafter immediately notified that the debug interrupt has been requested, the execution unit performs the save operation for a program counter and a program status word, and then, moves to the operation of the debug interrupt.