EP0265180A2
Expired / Lapsed
EP
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Multiplier in a galois field
Assignee: Panasonic Holdings Corp
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Filing: 1987-10-15
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Granted: —
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Expires: 2007-10-15
Abstract
Abstract A circuit effects regular multiplication of two field elements in a Galois field GF(2<m>). Each of the field elements is expressed by an m-bit binary member. The two field elements are applied to a binary multiplier array which generates (2m - 1)-bit partial prodcuts. The partial products are divided by a generator polynomial of the Galois field to produce final m-bit binary products.
Inventors
- 👤 Michihiro Matsumoto
- 👤 Kazuhiro Murase
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 08:30
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151; G06F7/60; G06F7/72; G06F7/724; H03M13/033
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
153 words
An apparatus for carrying out multiplication of field elements P = Σp i •a', Q = Σq i • a' (i = 0 through m - 1) in a Galois field GF(2 m ) whose generator polynomial is g(x) = x m + Σk i •x' (i = 0 through m - 1) comprising: a binary multiplier array supplied with the field elements P, Q for generating partial products R = Σr n •α n (n = 0 through 2m - 2) where r n = Ep u• q v for all n = u + v (u = 0 through m - 1 < n and v = 0 through m - 1 < n); and a polynomial reducer supplied with the partial products R for generating final products S = Σs i •α' (i = 0 through m - 1) through division of the partial products R by the generator polynomial.
Claim 2
Independent Claim
153 words
An apparatus for carrying out multiplication of field elements P = Σp i •a', Q = Σq i • a' (i = 0 through m - 1) in a Galois field GF(2 m ) whose generator polynomial is g(x) = x m + Σk i •x' (i = 0 through m - 1) comprising: a binary multiplier array supplied with the field elements P, Q for generating partial products R = Σr n •α n (n = 0 through 2m - 2) where r n = Ep u• q v for all n = u + v (u = 0 through m - 1 < n and v = 0 through m - 1 < n); and a polynomial reducer supplied with the partial products R for generating final products S = Σs i •α' (i = 0 through m - 1) through division of the partial products R by the generator polynomial.
Claim 3
Dependent Claim
38 words
An apparatus according to claim 1, wherein said binary multiplier array comprises AND gates each for effecting an AND operation of p i •q i and exclusive-OR gates for effecting bit addition of outputs from said AND gates.
Claim 4
Dependent Claim
61 words
An apparatus according to claim 1, wherein said polynomial reducer comprises a plurality of exclusive-OR gates for developing terms of α 2m-2 through α m of the partial products R to terms of α m- ' through a O thereof and effecting bit addition of the developed terms and the terms of α m-1 through a° of the partial products R.
Claim 5
Dependent Claim
71 words
An apparatus according to claim 1, wherein said polynomial reducer comprises a plurality of exclusive-OR gates arranged for developing each term α n of the partial products R to terms of α n-1 through α n-m thereof in repeated cycles from n = 2m - 2 to m, thereby developing terms of α 2m-2 through α m of the partial products R to terms of α m-1 through α 0 thereof.
Claim 6
Dependent Claim
36 words
An apparatus according to claim 4, wherein said polynomial reducer further includes AND gates connected so that one input of each of the AND gates is controlled by a coefficient k i of the generator polynomial.
References Cited (Backward Citations)
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