EP0265047A1
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EP
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Dual domino CMOS logic circuit, including complementary vectorization and integration
Assignee: AT&T Inc
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Filing: 1987-08-18
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Granted: —
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Expires: 2007-08-18
Abstract
Abstract At each stage of a domino CMOS logic circuit, the output signal Y 1 and its inversion Y are separately generated in mutually complementary first and second logic networks in each such stage. These outputs are then used as inputs for succeeding domino logic stages. In this way, all inputs are guaranteed to be low at the end of the precharging phase as is desired for all inputs to all domino logic.
Inventors
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 13:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; H03K19/20; H03K19/21; H03K19/215
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
82 words
A domino CMOS logic circuit CHARACTERIZED BY a dual domino CMOS logic gate (100) which comprises first and second complementary domino CMOS logic gate portions including first and second arrays, respectfully, of driver transistors (31, 32, 41, 42 and 71, 72, 81, 82) that are separately interconnected for providing first and second complementary output signals (Yi and Y i), respectively, in response to a plurality of input vectors (X and X ) applied to the first and second arrays of driver transistors.
Claim 2
Dependent Claim
82 words
A domino CMOS logic circuit CHARACTERIZED BY a dual domino CMOS logic gate (100) which comprises first and second complementary domino CMOS logic gate portions including first and second arrays, respectfully, of driver transistors (31, 32, 41, 42 and 71, 72, 81, 82) that are separately interconnected for providing first and second complementary output signals (Yi and Y i), respectively, in response to a plurality of input vectors (X and X ) applied to the first and second arrays of driver transistors.
Claim 3
Dependent Claim
53 words
A circuit according to claim 1 FURTHER CHARACTERIZED BY second and third dual domino CMOS logic gates, the set of input signals applied to the arrays of the third stage comprising both the first and second output signals of the first stage and the first and second output signals of the second stage.
Claim 4
Dependent Claim
30 words
The domino circuit of claim 2 in which the first and second output signals of each of the gates are the XOR and XNOR functions, respectively, of the input vectors.
References Cited (Backward Citations)
EP0147598A1
Cited
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