Dynamic RAM cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes

Claim 1

A one-device dynamic random access memory cell, comprising a trench (20) formed in an exposed surface of a semiconductor substrate, said trench being filled with at least a first conductive layer (22) and at least one dielectric layer (26)for isolating said first conductive layer from said substrate; at least one transistor device disposed on a portion of said substrate adjacent one side of said trench, said transistor having first (38) and second (36) conducting electrodes formed within said surface of said substrate to define a channel region therebetween and a third control electrode (34) disposed above and insulated (34A) from said channel region; characterized in that at least a portion of said first conductive layer extends above the surface of the substrate to define a mandrel structure which is contacted by a sidewall-defined bridge contact (30) disposed on said mandrel structure, said bridge contact having a vertical portion in contact with said portion of said first conductive layer (22) extending above said surface of said substrate, and a horizontal portion in contact with one of said control electrodes (36) of said at least one transistor device.

Claim 14

A method for forming a dynamic random access memory cell in an exposed surface of a semiconductor substrate, comprising the steps of: forming an elongated trench (20) in the exposed surface of the substrate, said trench having substan­tially vertical sidewalls and a bottom; coating said sidewalls and said bottom of said trench with at least one dielectric layer (26); forming at least a first polysilicon layer (22) within said trench, said first polysilicon layer being doped with dopant ions of a first conductivity type, said first polysilicon layer, said dielectric layer, and the substrate combining to provide a storage capacitance on each of said sidewalls of said trench, characterized by the steps of etching the substrate and said dielectric layer so that said first polysilicon layer is exposed to form a mandrel structure that projects above the surface of the substrate, said mandrel structure having an upper surface and sidewalls; forming a layer of insulating material (28,28A) on said upper surface of said first polysilicon layer, said insulating material having a lateral portion that extends beyond said sidewalls of said mandrel; coating a second polysilicon layer (30A) on the substrate; etching said second polysilicon layer so that a vertical portion (30) thereof remains on said sidewalls of said mandrel structure and a horizontal portion (30) thereof remains on the substrate, said horizontal portion being disposed beneath said lateral portion of said insulating material and having a lateral length commensurate therewith; heating the substrate so that dopant ions from said first polysilicon layer diffuse into said vertical portion of said second polysilicon layer, and at least a portion of said diffused dopant ions diffuse from said horizontal portion of said second polysilicon layer into an underlaying portion of the substrate to form a first diffused region therein (36); etching undoped portions of said second polysilicon layer (30A,B) by exposure to an etchant that does not appreciably attack doped portions thereof; forming a gate electrode (34) adjacent to said second polysilicon layer, and implanting ions into a portion of said substrate adjacent said gate electrode to form a second diffused region (38) in the substrate, said gate electrode overlaying a portion of the substrate between said first (36) and second (38) diffused regions so as to form a transistor device adjacent to said trench, said doped portions of said second polysilicon layer coupling said first diffused region (36) to said first polysilicon layer.

Claim 15

A method for forming a dynamic random access memory cell in an exposed surface of a semiconductor substrate, comprising the steps of: forming an elongated trench (20) in the exposed surface of the substrate, said trench having substan­tially vertical sidewalls and a bottom; coating said sidewalls and said bottom of said trench with at least one dielectric layer (26); forming at least a first polysilicon layer (22) within said trench, said first polysilicon layer being doped with dopant ions of a first conductivity type, said first polysilicon layer, said dielectric layer, and the substrate combining to provide a storage capacitance on each of said sidewalls of said trench, characterized by the steps of etching the substrate and said dielectric layer so that said first polysilicon layer is exposed to form a mandrel structure that projects above the surface of the substrate, said mandrel structure having an upper surface and sidewalls; forming a layer of insulating material (28,28A) on said upper surface of said first polysilicon layer, said insulating material having a lateral portion that extends beyond said sidewalls of said mandrel; coating a second polysilicon layer (30A) on the substrate; etching said second polysilicon layer so that a vertical portion (30) thereof remains on said sidewalls of said mandrel structure and a horizontal portion (30) thereof remains on the substrate, said horizontal portion being disposed beneath said lateral portion of said insulating material and having a lateral length commensurate therewith; heating the substrate so that dopant ions from said first polysilicon layer diffuse into said vertical portion of said second polysilicon layer, and at least a portion of said diffused dopant ions diffuse from said horizontal portion of said second polysilicon layer into an underlaying portion of the substrate to form a first diffused region therein (36); etching undoped portions of said second polysilicon layer (30A,B) by exposure to an etchant that does not appreciably attack doped portions thereof; forming a gate electrode (34) adjacent to said second polysilicon layer, and implanting ions into a portion of said substrate adjacent said gate electrode to form a second diffused region (38) in the substrate, said gate electrode overlaying a portion of the substrate between said first (36) and second (38) diffused regions so as to form a transistor device adjacent to said trench, said doped portions of said second polysilicon layer coupling said first diffused region (36) to said first polysilicon layer.

Claim 17

The method as of forming a memory cell recited in claims 12 or 13, wherein after said step of forming said first polysilicon layer, the method further comprises the steps of: coating said first polysilicon layer (22) with a layer of doped silicon oxide (62) having dopant ions of a first conductivity type; selectively removing lateral portions of said doped silicon oxide along said sides of said trench; annealing the substrate to drive said dopant ions from said layer of doped silicon oxide into said first layer of polysilicon, said dopant ions laterally diffusing along said first polysilicon layer; removing said layer of doped silicon oxide (62); and exposing (64) said first layer of polysilicon to an etchant that removes undoped portions of said first layer of polysilicon without appreciably attacking doped portions of said first layer of polysilicon.

Claim 20

A method for forming a dynamic random access memory array of one-device memory cells, comprising the steps of: forming an elongated trench (20) in an exposed surface of a semiconductor substrate; filling said trench with at least a first dielectric layer (26) and at least a first doped polysilicon layer (22), characterized in that an upper portion of said first polysilicon layer projecting above said surface of said semiconductor substrate to form a mandrel structure thereon; providing a plurality of sidewall-defined bridge contacts (30) on each side of said mandrel structure, said bridge contacts being disposed in a spaced relationship along each side of said trench, each of said bridge contacts having a vertical portion that contacts said mandrel structure and a horizontal portion that contacts an adjacent portion of said surface of said semiconductor substrate, said bridge contacts being formed of a second polysilicon layer coated on said mandrel, wherein said substrate is annealed so that dopant ions from said first polysilicon layer diffuse into said vertical portion of each of said bridge contacts and at least a portion of said diffused dopant ions diffuse from said horizontal portion of said second polysilicon layer into said adjacent portion of said semiconductor substrate to form a plurality first diffusion regions therein (36), undoped portions of said second polysilicon layer being removed by exposure to an etchant that does not appreciably attack said doped portions thereof; coating an insulating layer on said mandrel, and etching said layer to form a sidewall-defined insulation layer (28,32) that insulates said plurality of sidewall-defined bridge contacts from overlaying layers; providing a plurality of sidewall-defined gate electrodes (34) formed of a third polysilicon layer coated on said mandrel, each of said sidewall-defined gate electrodes overlaying a respective one of said sidewall-defined bridge contacts; and forming a plurality of second diffusion regions (38) in said substrate, said plurality of sidewall-defined gate electrodes overlaying portions of said substrate between said plurality of first (36) and second (38) diffusion regions to provide a plurality of transistor devices disposed in a spaced relationship along each side of said trench, said trench providing respective storage capacitors to each of said transistor devices.

Claim 21

A method for forming a dynamic random access memory array of one-device memory cells, comprising the steps of: forming an elongated trench (20) in an exposed surface of a semiconductor substrate; filling said trench with at least a first dielectric layer (26) and at least a first doped polysilicon layer (22), characterized in that an upper portion of said first polysilicon layer projecting above said surface of said semiconductor substrate to form a mandrel structure thereon; providing a plurality of sidewall-defined bridge contacts (30) on each side of said mandrel structure, said bridge contacts being disposed in a spaced relationship along each side of said trench, each of said bridge contacts having a vertical portion that contacts said mandrel structure and a horizontal portion that contacts an adjacent portion of said surface of said semiconductor substrate, said bridge contacts being formed of a second polysilicon layer coated on said mandrel, wherein said substrate is annealed so that dopant ions from said first polysilicon layer diffuse into said vertical portion of each of said bridge contacts and at least a portion of said diffused dopant ions diffuse from said horizontal portion of said second polysilicon layer into said adjacent portion of said semiconductor substrate to form a plurality first diffusion regions therein (36), undoped portions of said second polysilicon layer being removed by exposure to an etchant that does not appreciably attack said doped portions thereof; coating an insulating layer on said mandrel, and etching said layer to form a sidewall-defined insulation layer (28,32) that insulates said plurality of sidewall-defined bridge contacts from overlaying layers; providing a plurality of sidewall-defined gate electrodes (34) formed of a third polysilicon layer coated on said mandrel, each of said sidewall-defined gate electrodes overlaying a respective one of said sidewall-defined bridge contacts; and forming a plurality of second diffusion regions (38) in said substrate, said plurality of sidewall-defined gate electrodes overlaying portions of said substrate between said plurality of first (36) and second (38) diffusion regions to provide a plurality of transistor devices disposed in a spaced relationship along each side of said trench, said trench providing respective storage capacitors to each of said transistor devices.