Apparatus and method for improving cache access throughput in pipelined processors

Claim 2

In a data processing system including an instruction unit, a main store storing system data, and a storage unit having a high speed cache storing a subset of the data retrieved from the main store, the instruction unit including a first register receiving instructions including address information in a pipeline fashion and subject to interlocks in which an interlocked instruction held in the first register is prevented from advancing in the pipeline during one or more cycles, the storage unit including at least one port for holding address information, and cache management logic for managing cache access in response to address information, and further including a selector for selecting address information from the one port in the storage unit or from the first register in the instruction unit for supplyu to the cache management logic in response to a priority signal, and selector control logic for assigning priority to the port and the first register and generating the priority signal to control storage unit utilization, an apparatus for improving storage unit utilization during interlocks, comprising: means, coupled to the first register, for generating a control signal during one cycle of an interlock if the interlocked instruction may require cache access; and means, responsive to the control signal and coupled to the selector control logic, for increasing the priority of the first register for supply to the cache management logic.

Claim 3

The apparatus of claim 1 further including: means, responsive to the control signal and the priority signal, for generating a prefetch signal indicating that address information from an interlocked instruction is being processed.

Claim 4

The apparatus of claim 1, wherein said means for increasing the priority of the first register assigns the highest priority to the first register in response to the control signal resulting in supply of the address information from the first register to the cache management logic.

Claim 5

The apparatus of claim 2, further including: means, in communication with the cache management logic, for signalling the instruction unit when the cache management logic retrieves valid data from the high speed cache; and means, responsive to the prefetch signal, for disabling the means for signalling the instruction unit.

Claim 6

The apparatus of claim 1, wherein the one cycle of an interlock in which the control signal is generated is the first cycle.

Claim 7

The apparatus of claim 1, wherein said instruction unit further includes: means for generating an interlock release signal when the interlocked instruction is released in the pipeline; and the selector control logic includes means responsive to the interlock release signal, for increasing the priority of the interlocked instruction in the first register for supply to the cache management logic when the interlock is released.

Claim 8

The apparatus of claim 1, wherein the cache management logic includes; means, responsive to selected address information, for detecting whether data identified by the selected address information is available in the cache; and means for retrieving data from main store when the data is unavailable.

Claim 9

The apparatus of claim 7, wherein the address information includes virtual addresses that require valid translations for cache access and the cache management logic further includes: means, responsive to selected address information, for detecting whether a valid translation is present in the storage unit for the selected address information; and means for retrieving a valid translation when a valid translation is not present.

Claim 10

In a data processing system including an instruction unit, a main store storing system data, and a storage unit having a high speed cache storing a subset of the data retrieved from the main store, the instruction unit including a first register receiving instructions including address information in a pipeline fashion and subject to interlocks in which an interlocked instruction held in the first register is prevented from advancing in the pipeline during one or more cycles, the storage unit including at least one port holding address information, and cache management logic for managing cache access in response to address information, and further including a selector for selecting address information from the one port in the instruction unit or from the first register in the instruction unit for supply to the cache management logic in response to a priority signal, and selector control logic for assigning priority to the one port and the first register and generating the priority signal to control storage unit utilization, a method for improving storage unit utilization during interlocks, comprising the steps of: detecting whether the interlocked instruction will require cache access during one cycle of the interlock; if the interlocked instruction will require cache access, then increasing the priority of the first register for supply of address information from the interlocked instruction to cache management logic during the one cycle of the interlock.

Claim 11

In a data processing system including an instruction unit, a main store storing system data, and a storage unit having a high speed cache storing a subset of the data retrieved from the main store, the instruction unit including a first register receiving instructions including address information in a pipeline fashion and subject to interlocks in which an interlocked instruction held in the first register is prevented from advancing in the pipeline during one or more cycles, the storage unit including at least one port holding address information, and cache management logic for managing cache access in response to address information, and further including a selector for selecting address information from the one port in the instruction unit or from the first register in the instruction unit for supply to the cache management logic in response to a priority signal, and selector control logic for assigning priority to the one port and the first register and generating the priority signal to control storage unit utilization, a method for improving storage unit utilization during interlocks, comprising the steps of: detecting whether the interlocked instruction will require cache access during one cycle of the interlock; if the interlocked instruction will require cache access, then increasing the priority of the first register for supply of address information from the interlocked instruction to cache management logic during the one cycle of the interlock.

Claim 12

The method of claim 9, further including the step of: generating a prefetch signal indicating that address information from an interlocked instruction is being processed.

Claim 13

The method of claim 10, further including the step of: preventing the cache management logic from supplying data to the instruction unit in resposne to the prefetch signal.

Claim 14

The method of claim 9, wherein the step of increasing the priority of the first register assigns the highest priority to the first register resulting in supply of the address information from the first register to the cache management logic.

Claim 15

The method of claim 9, wherein the one cycle of an interlock is the first cycle.

Claim 16

The method of claim 9, further including the steps of: generating an interlock release signal when the interlocked instruction is released in the pipeline; and increasing the priority of the interlocked instruction in the first register for supply to the cache management logic in response to interlock release signal.