EP0264064A2
Expired / Lapsed
EP
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Word synchronizer
Assignee: NEC Corp
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Filing: 1987-10-08
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Granted: —
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Expires: 2007-10-08
Abstract
Abstract For establishing word synchronization between a data bit stream of N-bit words and the timing of syndrome calculation, a count value is incremented in response to the bit timing of the words and generating a hunting pulse (14a) for every count of N bits and a load timing pulse at every count of C bits. Syndrome calculation (11) is performed on the N-bit words in response to the hunting pulse to derive a syndrome when each of the N-bit words is out of synchronization with the timing of the calculation. The syndrome is latched (12) for a word interval and a first enabling signal (12b) is generated in response to the latching of the syndrome. Syndrome generating words are counted (13) to generate a second enabling signal (13a) when the count provides a valid indication that the word timing of the calculation is out of sync with the data hit stream. A copy of the hunting pulse is generated and delayed (15) for a period of M bits when the first and second enabling signals are simultaneously present (16) to cause syndrome calculation to be performed on the N-bit words, where the N and M integers are relatively prime and the integer C is smaller than integer M and greater than unity. The point of initialization is shifted for each syndrome calculation from one bit to another in search of the beginning of a word. Because of the "relatively prime" relationship of the integers N and M, all the bits of incoming data bit stream are examined in the search.
Inventors
- 👤 Shigeki C/O Nec Corporation Maeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 21:26
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/33
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
207 words
A method for establishing synchronism between a data bit stream of N-bit words encoded with an error correcting code and the timing of syndrome calculation, comprising the steps of: a) incrementing a count in response to the bit timing of said words and generating a hunting pulse for every count of N bits and a load timing pulse at every count of C bits, where the integer C is greater then unity; b) performing the syndrome calculation on said N-bit words in response to said hunting pulse and deriving a syndrome when each of said N-bit words is out of synchronization with the timing of said calculation; c) storing said syndrome and generating a first enabling signal in response to said load timing pulse; d) counting words which generate said syndrome and generating a second enabling signal when the count indicates an out-of-word synchronization; and e) delaying a copy of said hunting pulse for a period of M bits when said first and second enabling signals are simultaneously present and causing the step (b) to additionally perform said calculation in response to said delayed copy, wherein the integer M is larger than the integer C and the integers M and N are relatively prime to each other.
Claim 2
Independent Claim
207 words
A method for establishing synchronism between a data bit stream of N-bit words encoded with an error correcting code and the timing of syndrome calculation, comprising the steps of: a) incrementing a count in response to the bit timing of said words and generating a hunting pulse for every count of N bits and a load timing pulse at every count of C bits, where the integer C is greater then unity; b) performing the syndrome calculation on said N-bit words in response to said hunting pulse and deriving a syndrome when each of said N-bit words is out of synchronization with the timing of said calculation; c) storing said syndrome and generating a first enabling signal in response to said load timing pulse; d) counting words which generate said syndrome and generating a second enabling signal when the count indicates an out-of-word synchronization; and e) delaying a copy of said hunting pulse for a period of M bits when said first and second enabling signals are simultaneously present and causing the step (b) to additionally perform said calculation in response to said delayed copy, wherein the integer M is larger than the integer C and the integers M and N are relatively prime to each other.
Claim 3
Dependent Claim
215 words
A word synchronizer adapted to receive a data bit stream of N-bit words encoded with an error correcting code, comprising: timing means for incrementing a count in response to the bit timing of said words and generating a hunting pulse for every count of N bits and a load timing pulse for every count of C bits, the integer C being greater than unity; syndrome calculator means for performing syndrome calculation on said N-bit words in response to said hunting pulse and deriving a syndrome when each of said N-bit words is out of synchronization with the timing of said calculation; syndrome latch means for storing said syndrome and generating a first enabling signal in response to said load timing pulse; word synchronization detector means for counting words which generate said syndrome and generating a second enabling signal when the count indicates an out-of-word synchronization; and shift register means having M stages for delaying a copy of said hunting pulse for a period of M bits when said first and second enabling signals are simultaneously present and causing said syndrome calculator means to additionally perform said calculation is response to said delayed copy, wherein the integer M is larger than the integer C and the integers M and N are relatively prime to each other.
Claim 4
Dependent Claim
215 words
A word synchronizer adapted to receive a data bit stream of N-bit words encoded with an error correcting code, comprising: timing means for incrementing a count in response to the bit timing of said words and generating a hunting pulse for every count of N bits and a load timing pulse for every count of C bits, the integer C being greater than unity; syndrome calculator means for performing syndrome calculation on said N-bit words in response to said hunting pulse and deriving a syndrome when each of said N-bit words is out of synchronization with the timing of said calculation; syndrome latch means for storing said syndrome and generating a first enabling signal in response to said load timing pulse; word synchronization detector means for counting words which generate said syndrome and generating a second enabling signal when the count indicates an out-of-word synchronization; and shift register means having M stages for delaying a copy of said hunting pulse for a period of M bits when said first and second enabling signals are simultaneously present and causing said syndrome calculator means to additionally perform said calculation is response to said delayed copy, wherein the integer M is larger than the integer C and the integers M and N are relatively prime to each other.
Claim 5
Dependent Claim
285 words
A word synchronizer adapted to receive a data bit stream of N-bit words encoded with an error correcting code, comprising: first resettable timing means for incrementing a count in response to the bit timing of said words and generating a hunting pulse for every count of N bits; shift register means having M stages for generating a copy of said hunting pulse and delaying the copy for a period of M bits, wherein the integers N and M are relatively prime to each other: gate means for generating an output in response to said delayed copy when enabled by first and second enabling signals; resettable syndrome calculator means arranged to be initialized in response to said hunting pulse and said output of the gate means for performing calculation on said N-bit words and deriving a syndrome when each of said N-bit words is out of word synchronization with the word timing of said calculation; second resettable timing means arranged to be initialized in response to said hunting pulse and said output of the gate means for incrementing a count in response to the bit timing of said words and generating a load timing pulse at every count of C bits, wherein the integer C is greater than unity and smaller than the integer M; syndrome latch means for storing said syndrome and supplying a signal as said first enabling signal to said gate means in response to said load timing pulse; and word sync detector means for counting words generating said syndrome and supplying a signal as said second enabling signal to said gate means when the count indicates that input data bit stream is said out of word synchronization with said syndrome calculator means.
Claim 6
Dependent Claim
285 words
A word synchronizer adapted to receive a data bit stream of N-bit words encoded with an error correcting code, comprising: first resettable timing means for incrementing a count in response to the bit timing of said words and generating a hunting pulse for every count of N bits; shift register means having M stages for generating a copy of said hunting pulse and delaying the copy for a period of M bits, wherein the integers N and M are relatively prime to each other: gate means for generating an output in response to said delayed copy when enabled by first and second enabling signals; resettable syndrome calculator means arranged to be initialized in response to said hunting pulse and said output of the gate means for performing calculation on said N-bit words and deriving a syndrome when each of said N-bit words is out of word synchronization with the word timing of said calculation; second resettable timing means arranged to be initialized in response to said hunting pulse and said output of the gate means for incrementing a count in response to the bit timing of said words and generating a load timing pulse at every count of C bits, wherein the integer C is greater than unity and smaller than the integer M; syndrome latch means for storing said syndrome and supplying a signal as said first enabling signal to said gate means in response to said load timing pulse; and word sync detector means for counting words generating said syndrome and supplying a signal as said second enabling signal to said gate means when the count indicates that input data bit stream is said out of word synchronization with said syndrome calculator means.
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