EP0263447A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method and apparatus for implementing a branch and return on address instruction in a digital data processing system
Assignee: International Business Machines Corp
•
Filing: 1987-10-02
•
Granted: —
•
Expires: 2007-10-02
Abstract
Abstract A digital data processor acts on a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. The operation code field of the branch and return on address instruction is into an instruction register, the memory exit address field of the loaded branch and return on address instruction is loaded into the address register and the memory entry address field of the branch and return on address instruction is loaded into the program counter. The next sequential address following the address of the current BAROA instruction is then stored in a register stack, and a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction is fetched and executed. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. The memory address in the program counter is compared with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.
Inventors
- 👤 Richard Stephen Crouse
- 👤 Randall Paul Boudreaux
- 👤 John Joseph Cazzolla, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 23:26
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/60; G06F8/65; G06F8/66; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3005; G06F9/30054; G06F9/32; G06F9/322; G06F9/323; G06F9/328; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
270 words
A method of operating a digital data processing system for enabling instructions in a read-write memory coupled to a data processor modify the code in a read only memory coupled to the data processors, such method being characterised by: loading into the read-write memory a branch and return on address instruction followed by one or more other instructions for modifying the read only memory code, such branch and return on address instruction including an operation code field, a read only memory entry address field and a read only memory exit address field; commencing execution of the read only memory instructions contained in the read only memory code in a sequential manner, such read only memory instructions including a branch and return on address instruction in the read-write memory; branching to the read-write memory when such branch instruction is reached and executing the branch and return on address instruction by returning to the read only memory and executing a sequence of read only memory instructions starting with the instruction residing at the entry address provided by the branch and return on address instruction; and comparing the address of each read only memory instruction with the exit address provided by the branch and return on address instruction for returning to the read-write memory and commencing execution of the read-write memory instructions following the branch and return on address instruction when the read only memory address becomes equal to the exit address, such read-write memory instructions including a branch instruction for branch back to the read only memory at the appropriate point to complete the desired modification of the read only memory code.
Claim 2
Independent Claim
270 words
A method of operating a digital data processing system for enabling instructions in a read-write memory coupled to a data processor modify the code in a read only memory coupled to the data processors, such method being characterised by: loading into the read-write memory a branch and return on address instruction followed by one or more other instructions for modifying the read only memory code, such branch and return on address instruction including an operation code field, a read only memory entry address field and a read only memory exit address field; commencing execution of the read only memory instructions contained in the read only memory code in a sequential manner, such read only memory instructions including a branch and return on address instruction in the read-write memory; branching to the read-write memory when such branch instruction is reached and executing the branch and return on address instruction by returning to the read only memory and executing a sequence of read only memory instructions starting with the instruction residing at the entry address provided by the branch and return on address instruction; and comparing the address of each read only memory instruction with the exit address provided by the branch and return on address instruction for returning to the read-write memory and commencing execution of the read-write memory instructions following the branch and return on address instruction when the read only memory address becomes equal to the exit address, such read-write memory instructions including a branch instruction for branch back to the read only memory at the appropriate point to complete the desired modification of the read only memory code.
Claim 3
Dependent Claim
272 words
An address mechanism in a digital data processing system for enabling instructions in a read-write memory coupled to a data processor to modify the code in a read only memory coupled to the data processor, such mechanism characterised by: means for loading into the read-write memory a branch and return on address instruction followed by one or more other instructions for modifying the read only memory code, such branch and return on address instruction including an operation code field, a read only memory entry address field and a read only memory exit address field; means for executing the read only memory instructions contained in the read only memory code in a sequential manner, such read only memory instructions including a branch instruction for causing a branch to the branch and return on address instruction to the read-write memory; means responsive to the branch and return on address instruction for returning to the read only memory and executing a sequence of read only memory instructions starting with the instruction residing at the entry address provided by the branch and return on address instruction, and means for comparing the address of each read only memory instruction with the exit address provided by the branch and return on address instruction for returning to the read-write memory and commencing execution of the read-write memory instructions following the branch and return on address instruction when the read only memory address becomes equal to the exit address, such read-write memory instructions including a branch instruction for branching back to the read only memory at the appropriate point to complete the desired modification of the read only memory code.
Claim 4
Dependent Claim
272 words
An address mechanism in a digital data processing system for enabling instructions in a read-write memory coupled to a data processor to modify the code in a read only memory coupled to the data processor, such mechanism characterised by: means for loading into the read-write memory a branch and return on address instruction followed by one or more other instructions for modifying the read only memory code, such branch and return on address instruction including an operation code field, a read only memory entry address field and a read only memory exit address field; means for executing the read only memory instructions contained in the read only memory code in a sequential manner, such read only memory instructions including a branch instruction for causing a branch to the branch and return on address instruction to the read-write memory; means responsive to the branch and return on address instruction for returning to the read only memory and executing a sequence of read only memory instructions starting with the instruction residing at the entry address provided by the branch and return on address instruction, and means for comparing the address of each read only memory instruction with the exit address provided by the branch and return on address instruction for returning to the read-write memory and commencing execution of the read-write memory instructions following the branch and return on address instruction when the read only memory address becomes equal to the exit address, such read-write memory instructions including a branch instruction for branching back to the read only memory at the appropriate point to complete the desired modification of the read only memory code.
Claim 5
Independent Claim
259 words
A method of operating a digital data processor having instruction and data processing elements including a program counter for holding the memory address of the instruction to be executed, an instruction register for receiving the operation code field of the instruction to be executed, a memory address register and a control unit for controlling the instruction and data processing elements in accordance with the operation code field residing in the instruction register characterised by the steps of: supplying to the digital data processor a branch and return on address instruction having an operation code field, a memory entry address field and a memory exit address field; loading the operation code field of the branch and return on address instruction into the instruction register; loading the memory exit address field of the branch and return on address instruction into the memory address register; loading the memory entry address field of the branch and return on address instruction into the program counter; fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction; incrementing the program counter each time an instruction is executed, such program counter providing the memory addresses of the instructions to be fetched; and comparing the memory address in the program counter with the exit address in the memory address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the memory address register.
Claim 6
Independent Claim
259 words
A method of operating a digital data processor having instruction and data processing elements including a program counter for holding the memory address of the instruction to be executed, an instruction register for receiving the operation code field of the instruction to be executed, a memory address register and a control unit for controlling the instruction and data processing elements in accordance with the operation code field residing in the instruction register characterised by the steps of: supplying to the digital data processor a branch and return on address instruction having an operation code field, a memory entry address field and a memory exit address field; loading the operation code field of the branch and return on address instruction into the instruction register; loading the memory exit address field of the branch and return on address instruction into the memory address register; loading the memory entry address field of the branch and return on address instruction into the program counter; fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction; incrementing the program counter each time an instruction is executed, such program counter providing the memory addresses of the instructions to be fetched; and comparing the memory address in the program counter with the exit address in the memory address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the memory address register.
Claim 7
Dependent Claim
287 words
A digital data processor having instruction and data processing elements including a program counter for holding the memory address of the instruction to be executed, an instruction register for receiving the operation code field of the instruction to be executed and a control unit for controlling the instruction and data processing elements in accordance with the operation code field residing in the instruction register, characterised by a branch and return on address mechanism comprising: means for supplying a branch and return on address instructions having an operation code field, a memory entry address field and a memory exit address field; means for loading the operation code field of the branch and return on address instruction into the instruction register; exit address register means; means for loading the memory exit address field of the branch and return on address instruction into the exit address register means; means for loading the memory entry address field of the branch and return on address instruction into the program counter; means for fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction; means for incrementing the program counter each time an instruction is executed, such program counter providing the memory addresses of the instructions to be fetched; means for comparing the memory address int he program counter with the memory address in the exit address register for producing an equality signal when these two memory addresses become equal to one another; and means responsive to the occurrence of an equality signal for causing a return instruction operation code to be loaded into the instruction register to serve as the next instruction to be executed.
Claim 8
Dependent Claim
287 words
A digital data processor having instruction and data processing elements including a program counter for holding the memory address of the instruction to be executed, an instruction register for receiving the operation code field of the instruction to be executed and a control unit for controlling the instruction and data processing elements in accordance with the operation code field residing in the instruction register, characterised by a branch and return on address mechanism comprising: means for supplying a branch and return on address instructions having an operation code field, a memory entry address field and a memory exit address field; means for loading the operation code field of the branch and return on address instruction into the instruction register; exit address register means; means for loading the memory exit address field of the branch and return on address instruction into the exit address register means; means for loading the memory entry address field of the branch and return on address instruction into the program counter; means for fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction; means for incrementing the program counter each time an instruction is executed, such program counter providing the memory addresses of the instructions to be fetched; means for comparing the memory address int he program counter with the memory address in the exit address register for producing an equality signal when these two memory addresses become equal to one another; and means responsive to the occurrence of an equality signal for causing a return instruction operation code to be loaded into the instruction register to serve as the next instruction to be executed.
Claim 9
Dependent Claim
33 words
A processor according to claim 4 wherein the means for supplying a branch and return on address instruction includes a memory mechanism coupled to the digital data processor for supplying operating instructions thereto.
Claim 10
Dependent Claim
65 words
A processor according to claim 4 or claim 5 wherein the means for comparing the memory address in the program counter with the memory address in the exit address register comprising a comparator circuit coupled to the program counter and to the exit address register for comparing the address value contained in the program counter with the address value contained in the exit address register.
Claim 11
Dependent Claim
97 words
A processor according to any one of claims 4 to 6 further including: means responsive to the loading of the branch and return on address operation code field into the instruction register for saving the address of the next following instruction in a return address register; and means responsive to the loading of the return instruction operation code into the instruction register for returning the saved instruction address from the return address register to the program counter for causing the digital data processor to fetch and execute the instruction following the branch and return on address instruction.
Claim 12
Dependent Claim
131 words
A processor according to any one of claims 4 to 7 wherein the means responsive to the occurrence of an equality signal for causing a return instruction operation code to be loaded into the instruction register includes: hardware circuit means for producing a return instruction operation code; a data bus for supplying the instruction operation codes fetched from memory; multiplexer circuit means for selectively coupling either the data bus or the return instruction hardware circuit means to the instruction register; and means responsive to the occurrence of an equality signal for causing the multiplexer circuit means for couple the return instruction hardware circuit means to the instruction register for enabling the return instruction operation code to be loaded into the instruction register to serve as the next instruction to be executed.
Claim 13
Dependent Claim
140 words
A processor according to claim 8 and further including: latch circuit means for indicating whether the branch and return on address function is in progress; circuit means responsive to the loading of the exit address into the exit address register for setting the latch circuit means to indicate that the branch and return on address function is in progress; circuit means responsive to the loading of the return instruction operation code into the instruction register for resetting the latch circuit means to indicate that the branch and return on address function is not in progress; and circuit means coupled to the latch circuit means and responsive to the state thereof for enabling the multiplexer circuit means to respond to the equality signal only when the latch circuit means indicates that the branch and return on address function is in progress.
Claim 14
Independent Claim
124 words
A method of using a read-write memory code patch for correcting a read only memory code bug comprising: branching from the read only memory code to the read-write memory code patch; obtaining from the read-write memory code patch a read only memory exit address specifying the first line of read only memory code containing the code bug; resuming normal execution of the read only memory code; comparing the read only memory exit address with the address of the next read only memory instruction to be executed; and branching to the read-write memory code patch and executing the remainder of the instruction therein when the address of the next read only memory instruction to be executed is equal to the read only memory exit address.
Claim 15
Independent Claim
124 words
A method of using a read-write memory code patch for correcting a read only memory code bug comprising: branching from the read only memory code to the read-write memory code patch; obtaining from the read-write memory code patch a read only memory exit address specifying the first line of read only memory code containing the code bug; resuming normal execution of the read only memory code; comparing the read only memory exit address with the address of the next read only memory instruction to be executed; and branching to the read-write memory code patch and executing the remainder of the instruction therein when the address of the next read only memory instruction to be executed is equal to the read only memory exit address.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.