EP0263287A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Forming a capacitor in an integrated circuit
Assignee: International Business Machines Corp
•
Filing: 1987-08-25
•
Granted: —
•
Expires: 2007-08-25
Abstract
Abstract A capacitor is formed in an integrated circuit at the same time as field effect transistors, by the successive steps of: forming a well (22) of a first conductivity type in a semiconductor substrate (21); forming a high concentration impurity region of a second conductivity type in the well to form a first capacitor plate (23) at the same time that the impurity regions for the sources and drains of the transistors are formed; forming an oxide layer (24) having access holes over the impurity region to form the capacitor dielectric at the same time that the oxide layer for the gates of the transistors is formed; forming a layer of high conductivity material (e.g. 26a) over the oxide layer to form a second capacitor plate; and forming a layer (25) of metallization over the oxide and impurity region in the access holes to provide electrical connection to the first capacitor plate (23).
Inventors
- 👤 Raymond Allen Muggli
- 👤 Terence Patrick Mccaffrey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 18:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/212; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/0133; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
160 words
A method of forming a capacitor (20) in an integrated circuit at the same time as field effect transistors are formed, the method comprising the successive steps of: forming a well (22) of a first conductivity type in a semiconductor substrate (21); forming a high concentration impurity region of a second conductivity type in the well to form a first capacitor plate (23) at the same time that the impurity regions for the sources and drains of the transistors are formed; forming an oxide layer (24) having access holes over the impurity region to form the capacitor dielectric at the same time that the oxide layer for the gates of the transistors is formed; forming a layer of high conductivity material (e.g. 26a) over the oxide layer to form a second capacitor plate; and forming a layer (25) of metallization over the oxide and impurity region in the access holes to provide electrical connection to the first capacitor plate (23).
Claim 2
Independent Claim
160 words
A method of forming a capacitor (20) in an integrated circuit at the same time as field effect transistors are formed, the method comprising the successive steps of: forming a well (22) of a first conductivity type in a semiconductor substrate (21); forming a high concentration impurity region of a second conductivity type in the well to form a first capacitor plate (23) at the same time that the impurity regions for the sources and drains of the transistors are formed; forming an oxide layer (24) having access holes over the impurity region to form the capacitor dielectric at the same time that the oxide layer for the gates of the transistors is formed; forming a layer of high conductivity material (e.g. 26a) over the oxide layer to form a second capacitor plate; and forming a layer (25) of metallization over the oxide and impurity region in the access holes to provide electrical connection to the first capacitor plate (23).
Claim 3
Dependent Claim
17 words
A method as claimed on claim 1, wherein the first and second conductivity types are the same.
Claim 4
Dependent Claim
23 words
A method as claimed in claim 2, wherein the conductivity type of the substrate is different from the first and second conductivity types.
Claim 5
Dependent Claim
16 words
A method as claimed in claim 1, wherein the first and second conductivity types are different.
Claim 6
Dependent Claim
16 words
A method as claimed in claim 4, wherein the substrate is of the second conductivity type.
Claim 7
Dependent Claim
15 words
A method as claimed in claim 5, wherein the second conductivity type is P type.
Claim 8
Dependent Claim
31 words
A method as claimed in claim 2, in which the first and second conductivity types are N type, the oxide layer is silicon dioxide, and the high conductivity material is polysilicon.
Claim 9
Independent Claim
50 words
A method of simultaneously forming a pair of capacitors in an integrated circuit, in which each capacitor is formed by a method as claimed in any preceding claim whereby the first capacitor plates of the pair of capacitors are, in operation of the integrated circuit, biased at the same voltage.
Claim 10
Dependent Claim
54 words
A method as claimed in claim 8, in which the pair of capacitors are formed at adjacent locations in the integrated circuit so that a third capacitor is comprised by the second capacitor plates of the pair of capacitors and the intervening first capacitor plates and the capacitor dielectric of the pair of capacitors.
Claim 11
Dependent Claim
22 words
An integrated circuit having field effect transistors and a capacitor or capacitors formed by a method as claimed in any preceding claim.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.