Sample rate conversion system having interpolation function

Claim 2

A sample rate conversion system having an interpolation function, said system comprising: a first digital data processing system (111), for outputting digital data obtained by sampling, in re­sponse to a clock signal of a first frequency, original data having a characteristic enabling linear inter­polation thereof; a second digital data processing system (113), for obtaining output data by sampling input data, in re­sponse to a clock signal of a second frequency; and sample rate conversion means (112) for receiving the digital data from said first digital data processing system (111), converting a sample rate of the digital data into a sample rate suitable for said second digital data processing system (113), and supplying the sample rate, as the input data, to said second digital data processing system (113). said sample rate conversion means (112) comprising interpolation means (128) for performing interpolation of two adjacent units of data of the digital data received from said first digital data processing system (111), and interpolation coef­ficient calculation means (124, 125) for calculating an interpolation coefficient, which is subsequently supplied to said interpolation means (128), in accord­ance with a phase relationship between the clock signals of the first and second frequencies.

Claim 3

A system according to claim 1, characterized in that said interpolation is a linear interpolation.

Claim 4

A system according to claim 1, characterized in that said interpolation means (128) comprises a variable filter (128).

Claim 5

A system according to claim 3, characterized in that said variable filter (128) comprises a first multiplier (281), for multiplying one of the two adja­cent units of data by a first interpolation coefficient, a second multiplier (282), for multiplying the other one of the two adjacent units of data by a second inter­polation coefficient, and an adder (283) for adding the resulting outputs from said first and second multipliers (281, 282).

Claim 6

A system according to claim 3, characterized in that said variable filter (128ʹ) comprises an operation circuit (284) for causing the difference of the two adjacent units of data (Xn, Xn+1), a multiplier (285) for multiplying the resulting output from said operation circuit by an interpolation coefficient (k), and an adder (286) for adding the resulting output from said multipler (285) and the latter (Xn+1) of the two adja­cent units of data.

Claim 7

A system according to claim 1, characterized in that said interpolation coefficient calculation means (124, 125) includes latch means (124) for latching (n+1) timing signals obtained by dividing one period of the clock signal of the first frequency by n , in response to the clock signal of the second frequency, and priority encoder means (125) for discriminating a relative phase between the clock signals of the first and second fre­quencies, in accordance with a specific pattern indicated by bit outputs from said latch means, so as to calculate a first interpolation coefficient k and a second inter­polation coefficient 1-k.

Claim 8

A system according to claim 6, characterized in that said system further includes interpolation coeffi­cient correcting means (131, 132, 133), which comprises latch means (131) for latching (n+1) timing signals obtained by dividing one period of the clock signal of the first frequency by n , in response to the clock signal of the first frequency, priority encoder means (132) for discriminating a relative phase between the clock signal of the first frequency and the (n+1) timing signals, in accordance with a specific pattern indicated by bit outputs from said latch means, so as to output an interpolation coefficient correcting signal, and correcting means (133) for correcting the first and second interpolation coefficients, in accordance with the interpolation coefficient correcting signal from said priority encoder means (132).

Claim 9

A sample rate conversion circuit for converting first digital data having a first clock frequency into second digital data having a second clock frequency, different from the first clock frequency, comprising: clock signal delay means (122), consisting of cascade-connected n delay stages, for delaying a first clock signal having the first clock frequency; latch means for latching (124), in response to a second clock signal, delayed clock signals for (n+1) phases output from said clock signal delay means (122); interpolation coefficient calculation means (125) for discriminating a relative phase between the first and second clock signals, in accordance with the latch output from said latch means (124) and the number of delay stages of said clock signal delay means (122), so as to calculate an interpolation coefficient for con­verting the first data into the second data by linear interpolation; and a variable filter (128) for linearly interpolating the first digital data, in accordance with the interpola­tion coefficient from said interpolation coefficient calculation means, to obtain the second digital data.

Claim 10

A sample rate conversion circuit for converting first digital data having a first clock frequency into second digital data having a second clock frequency, different from the first clock frequency, comprising: clock signal delay means (122), consisting of cascade-connected n delay stages, for delaying a first clock signal having the first clock frequency; latch means for latching (124), in response to a second clock signal, delayed clock signals for (n+1) phases output from said clock signal delay means (122); interpolation coefficient calculation means (125) for discriminating a relative phase between the first and second clock signals, in accordance with the latch output from said latch means (124) and the number of delay stages of said clock signal delay means (122), so as to calculate an interpolation coefficient for con­verting the first data into the second data by linear interpolation; and a variable filter (128) for linearly interpolating the first digital data, in accordance with the interpola­tion coefficient from said interpolation coefficient calculation means, to obtain the second digital data.

Claim 11

A sample rate conversion circuit for converting first digital data having a first clock frequency into second digital data having a second clock frequency, different from the first clock frequency, comprising: clock signal delay means (122), consisting of cascade-connected n delay stages, for delaying a first clock signal having the first clock frequency; first latch means (124) for latching, in response to a second clock signal, delayed clock signals for (n+1) phases output from said clock signal delay means (122); interpolation coefficient calculation means (125) for discriminating a relative phase between the first and second clock signals, in accordance with the latch output from said first latch means (124) and the number of delay stages of said clock signal delay means (122), so as to calculate an interpolation coefficient for con­verting the first data into the second data by linear interpolation; second latch means (131) for latching the signals for the (n+1) phases, in response to the first clock signal; relative phase detection means (132) for detecting a relative phase between the first clock signal and the delayed clock signals for the (n+1) phases, in accordance with the latch output from said second latch means (131) and the number of delay stages of said clock signal delay means (122); normalization means (133) for normalizing the calculation output from said interpolation coefficient calculation means (125), in accordance with the detection output from said relative phase detection means (132); and a variable filter (128) for linearly interpolating the first digital data, in accordance with the normalized output from said normalization means (133), to obtain the second digital data.

Claim 12

A sample rate conversion circuit for converting first digital data having a first clock frequency into second digital data having a second clock frequency, different from the first clock frequency, comprising: clock signal delay means (122), consisting of cascade-connected n delay stages, for delaying a first clock signal having the first clock frequency; first latch means (124) for latching, in response to a second clock signal, delayed clock signals for (n+1) phases output from said clock signal delay means (122); interpolation coefficient calculation means (125) for discriminating a relative phase between the first and second clock signals, in accordance with the latch output from said first latch means (124) and the number of delay stages of said clock signal delay means (122), so as to calculate an interpolation coefficient for con­verting the first data into the second data by linear interpolation; second latch means (131) for latching the signals for the (n+1) phases, in response to the first clock signal; relative phase detection means (132) for detecting a relative phase between the first clock signal and the delayed clock signals for the (n+1) phases, in accordance with the latch output from said second latch means (131) and the number of delay stages of said clock signal delay means (122); normalization means (133) for normalizing the calculation output from said interpolation coefficient calculation means (125), in accordance with the detection output from said relative phase detection means (132); and a variable filter (128) for linearly interpolating the first digital data, in accordance with the normalized output from said normalization means (133), to obtain the second digital data.