Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits

Claim 2

In an integrated circuit fabrication process, a method of making a multi-layer metallization struc­ture including a conductor metal and a barrier metal comprising a composition of titanium-tungsten which can include an amount of contaminant metal ions, the method comprising: depositing a layer of the barrier metal on a sur­face of a semiconductor substrate; depositing a layer of the conductor metal on the barrier metal layer, the barrier metal layer separating the conductor metal from said surface; patterning the conductor and barrier metal layers to define said structure along the substrate surface as a predetermined pattern of conductive interconnects and gate contacts having a pair of opposite sidewalls; depositing a layer of a gettering composition over the substrate including in contact with each of the sidewalls of the metallization structure, the gettering composition being selected to react with and bind any of the contaminant metal ions coming in contact there­with; selectively removing a portion of the gettering composition layer to expose a top surface of the con­ductor metal layer while leaving a sidewall portion of the gettering composition layer contacting the sub­strate along each of the sidewalls of the metallization structure; removing a portion of the contaminant metal ions from the barrier metal so as to reduce the amount of said ions available to contaminate the semiconductor substrate; and depositing and adhering a layer of an insulative material onto the exposed conductor metal and the side­wall layers of the gettering composition.

Claim 3

A method according to claim 1 in which the contaminant metal ions include sodium ions.

Claim 4

A method according to claim 2 in which the gettering composition is phosphorus-silicate glass.

Claim 5

A method according to claim 1 in which the step of depositing and adhering an insulative layer includes depositing a layer of silicon nitride upon and in contact with the exposed conductor metal and the sidewall portions of the gettering composition.

Claim 6

A method according to claim 4 including depositing a layer of silicon oxide onto the layer of silicon nitride.

Claim 7

A method according to claim 1 in which the conductor metal is an alloy comprising a noble metal.

Claim 8

A method according to claim 6 in which the noble metal is gold.

Claim 9

A method according to claim 1 in which the step of selectively removing includes anisotropically etching the gettering composition layer.

Claim 10

A method according to claim 1 in which the gettering composition layer is a phosphorus-silicate glass and the step of selectively removing includes reactive ion etching said layer.

Claim 11

A method acccording to claim 1 including selectively etching the barrier metal after deposition of the conductor metal and patterning so as to form the sidewalls of the metallization structure with a recess adjacent the substrate surface, and chemical vapor depositing the gettering composition.

Claim 12

A method according to claim 1 in which the removing step includes annealing the circuit to mobi­lize said metal ions and cause a migration thereof into contact with the gettering composition sidewall layers.

Claim 13

A method according to claim 11 in which the substrate is annealed at about 400°C for about 30 min­utes.

Claim 14

In an integrated circuit fabrication process, a method of making a multi-layer metallization struc­ture including a conductor metal and a barrier metal comprising a composition of titanium-tungsten which can include an amount of contaminant sodium ions, the method comprising: depositing a layer of the barrier metal on a sur­face of a semiconductor substrate; depositing a layer of the conductor metal on the barrier metal layer, the barrier metal layer separating the conductor metal from said surface; patterning the conductor and barrier metal layers to define said structure along the substrate surface as a predetermined pattern of conductive interconnects and gate contacts having a pair of opposite sidewalls; depositing a layer of a gettering composition over the substrate including in contact with each of the sidewalls of the metallization structure, the gettering composition being selected to react with and bind any of the contaminant sodium ions coming in contact there­with; selectively removing a portion of the gettering composition layer to expose a top surface of the con­ductor metal layer while leaving a sidewall portion of the gettering composition layer contacting the sub­strate along each of the sidewalls of the metallization structure; annealing the circuit to mobilize said sodium ions and cause a migration thereof into contact with the gettering composition sidewall portions so as to reduce the amount of sodium ions available to contaminate the semiconductor substrate; and depositing and adhering a layer of an insulative material onto the exposed conductor metal and the side­wall portions of the gettering composition.

Claim 15

In an integrated circuit fabrication process, a method of making a multi-layer metallization struc­ture including a conductor metal and a barrier metal comprising a composition of titanium-tungsten which can include an amount of contaminant sodium ions, the method comprising: depositing a layer of the barrier metal on a sur­face of a semiconductor substrate; depositing a layer of the conductor metal on the barrier metal layer, the barrier metal layer separating the conductor metal from said surface; patterning the conductor and barrier metal layers to define said structure along the substrate surface as a predetermined pattern of conductive interconnects and gate contacts having a pair of opposite sidewalls; depositing a layer of a gettering composition over the substrate including in contact with each of the sidewalls of the metallization structure, the gettering composition being selected to react with and bind any of the contaminant sodium ions coming in contact there­with; selectively removing a portion of the gettering composition layer to expose a top surface of the con­ductor metal layer while leaving a sidewall portion of the gettering composition layer contacting the sub­strate along each of the sidewalls of the metallization structure; annealing the circuit to mobilize said sodium ions and cause a migration thereof into contact with the gettering composition sidewall portions so as to reduce the amount of sodium ions available to contaminate the semiconductor substrate; and depositing and adhering a layer of an insulative material onto the exposed conductor metal and the side­wall portions of the gettering composition.

Claim 16

An integrated circuit process according to claim 13 in which the gettering composition is phospho­rus-silicate glass, the depositing and adhering step including depositing an adhesion layer of silicon nitride onto the exposed conductor metal and the phos­phorus-silicate glass sidewalls and depositing an insu­lative silicon dioxide layer onto the silicon nitride layer.

Claim 17

An integrated circuit process according to claim 13 including annealing the substrate for a dura­tion and at a temperature sufficient to reduce field voltage shift to a range less than 500 millivolts per 1000 Å of thickness of the insulative material.

Claim 18

An integrated circuit process according to claim 15 in which the annealing duration is about 30 minutes at a temperature of about 400°C.

Claim 19

An integrated circuit comprising: a semiconductor substrate having a substrate sur­face; a multi-level metallization structure including a barrier metal layer contacting the substrate surface and a conductive metal layer contacting the barrier metal and thereby spaced from the substrate surface, said layers being patterned to form a predetermined arrangement of conductive interconnections and gate contacts on the substrate surface and the metallization structure having opposite sidewalls intersecting the substrate surface; a glass composition layer covering and contacting the conductive and barrier metal layer along each of the sidewalls thereof, the glass composition including means for gettering metal ions; an insulative layer contiguously covering the metallization structure, the glass composition layers and adjoining portions of the substrate; and adhesion means for adhering the insulative layer to the metallization structure and glass composition layers; the conductive metal layer having a top surface devoid of said glass composition and the adhesion means contacting the top surface to adhere the insulative layer to the conductive metal layer and thereby clamp the glass composition layers in contact with the metal­lization.

Claim 20

An integrated circuit comprising: a semiconductor substrate having a substrate sur­face; a multi-level metallization structure including a barrier metal layer contacting the substrate surface and a conductive metal layer contacting the barrier metal and thereby spaced from the substrate surface, said layers being patterned to form a predetermined arrangement of conductive interconnections and gate contacts on the substrate surface and the metallization structure having opposite sidewalls intersecting the substrate surface; a glass composition layer covering and contacting the conductive and barrier metal layer along each of the sidewalls thereof, the glass composition including means for gettering metal ions; an insulative layer contiguously covering the metallization structure, the glass composition layers and adjoining portions of the substrate; and adhesion means for adhering the insulative layer to the metallization structure and glass composition layers; the conductive metal layer having a top surface devoid of said glass composition and the adhesion means contacting the top surface to adhere the insulative layer to the conductive metal layer and thereby clamp the glass composition layers in contact with the metal­lization.

Claim 21

An integrated circuit according to claim 17 in which the barrier metal is a composition of tita­nium-tungsten.

Claim 22

An integrated circuit according to claim 17 in which the glass composition is phosphorous-silicate glass.

Claim 23

An integrated circuit according to claim 17 in which the conductive metal is gold, the insulative layer is silicon dioxide, and the adhesion means is a layer of silicon nitride.

Claim 24

An integrated circuit according to claim 17 in which the barrier metal is a composition of tita­nium-tungsten and the glass composition is phosphorous-­silicate glass.

Claim 25

An integrated circuit according to claim 21 having a field voltage shift in the range less than 500 millivolts per 1000 Å of thickness of the insulative layer.

Claim 26

An integrated circuit according to claim 21 having an inversion voltage of at least 15 volts.