Data processor having a high speed data transfer function

Claim 2

A data processor comprising a data processing means for supplying a predetermined length of data to be transferred and generating a transfer start signal, a data transferring means receiving the predetermined length of data to be transferred from the data processing means for transferring the same data through a data transferring terminal, means for detecting a transfer inhibit signal from an external, means receiving the transfer start signal from the data processing means for temporarily holding the same transfer start signal, and transfer control means associated to the data transferring means for causing the data transferring means to stop the trasnfer of data during the period the transfer inhibiting signal is active and allowing the data transferring unit to start the transfer of data at least when the transfer inhibiting signal becomes inactive after the transfer start signal is generated.

Claim 3

A data processor claimed in Claim 1 wherein the data transferring means includes a shift register having a parallel input coupled through an internal data bus to the data processing means to receive a predetermined length of parallel data from the data processing means, the shift register having a serial output coupled to the data transfer terminal, and a clock control means for generating a serial clock to a clock transferring terminal and to the shift register so as to cause the data held in the shift register to be outputted from the serial output of the shift register in synchronism with the serial clock.

Claim 4

A data processor claimed in Claim 2 wherein the transfer inhibit signal detecting means includes a busy detector responsive to a busy signal from a data receiving device for generating a busy detection signal, wherein the transfer start signal holding means includes a flip-flop adapted to be set by the transfer start signal so as to generate a start memory signal, and wherein the transfer control means includes a transfer start controller receiving the busy detection signal and the start memory signal for generating, when the busy detection signal is inactive and the start memory signal is active, a start trigger signal to the clock control means and the flip-flop, so that the clock control means causes the shift register to output the serial data and the flip-flop is reset.

Claim 5

A data processor claimed in Claim 3 wherein the busy detector is connected at its input to a busy signal terminal independent of the data transfer terminal.

Claim 6

A data processor claimed in Claim 3 wherein the busy detector is connected at its input to the data transfer terminal, and wherein the serial output of the shift register is connected to an input of an buffer circuit whose output is connected to the data transfer terminal, the output of the buffer circuit assuming either a high impedance condition or a low level condition in response to the input so that when the data transfer terminal is connected to a pulled-up data transfer line, the data transfer line is selectively brought either into a low level or into a high level in accordance with the output condition of the buffer circuit.

Claim 7

A data processor claimed in Claim 1 wherein the transfer inhibit signal detecting means includes a busy detector responsive to a busy signal from a data receiving device for generating a busy detection signal, wherein the transfer start signal holding means includes a flip-flop adapted to be set by the transfer start signal so as to generate a start memory signal, and wherein the transfer control means includes a transfer start controller receiving the busy detection signal and the start memory signal for generating, when the busy detection signal is inactive and the start memory signal is active, a start trigger signal to the data transferring means and the flip-flop, so that the data transferring means starts to output the serial data and the flip-flop is reset.

Claim 8

A data processor claimed in Claim 6 wherein the busy detector is connected at its input to a busy signal terminal independent of the data transfer terminal.

Claim 9

A data processor claimed in Claim 6 wherein the busy detector is connected at its input to the data transfer terminal, and wherein the serial output of the data transferring means is connected to an input of an buffer circuit whose output is connected to the data transfer terminal, the output of the buffer circuit assuming either a high impedance condition or a low level condition in response to the input so that when the data transfer terminal is connected to a pulled-up data transfer line, the data transfer line is selectively brought either into a low level or into a high level in accordance with the output condition of the buffer circuit.

Claim 10

A data processor comprising a data receiving means for receiving a predetermined length of data through a data transfer terminal and generating a reception end signal when the predetermined length of data has been received, a data processing means coupled to the data receiving means for processing the received data and generating a transfer acknowledge signal when the processing of the received data has been completed, and means receiving the reception end signal and the transfer acknowledge signal for generating a transfer inhibit signal after the reception end signal has been generated until the transfer acknowledge signal has been generated.

Claim 11

A data processor comprising a data receiving means for receiving a predetermined length of data through a data transfer terminal and generating a reception end signal when the predetermined length of data has been received, a data processing means coupled to the data receiving means for processing the received data and generating a transfer acknowledge signal when the processing of the received data has been completed, and means receiving the reception end signal and the transfer acknowledge signal for generating a transfer inhibit signal after the reception end signal has been generated until the transfer acknowledge signal has been generated.

Claim 12

A data processor claimed in Claim 9 wherein the data receiving means includes a shift register having a serial input coupled to the data transfer terminal and a parallel output coupled through an internal data bus to the data processing means, and a clock control means receiving a serial clock through a clock transferring terminal for causing the transfer data to be serially inputted to the shift register in synchronism with the received clock.

Claim 13

A data processor claimed in Claim 10 wherein the transfer inhibit signal generating means includes a flip-­flop having a set input connected to receive the reception end signal and a reset input connected to receive the transfer acknowledge signal, the flip-flop also having an inverted output generating a busy signal which is rendered active when the reception end signal becomes active and is rendered inactive when the transfer acknowledge signal becomes active.

Claim 14

A data processor claimed in Claim 11 wherein the inverted output of the flip-flop is connected to a busy signal terminals independent of the data transfer terminal.

Claim 15

A data processor claimed in Claim 11 wherein the clock control means is adapted to generate a synchronizing clock after the predetermined length of data has been received, and further including a synchronizing flip-flop receiving the inverted output of the busy signal generating flip-flop and the synchronizing clock for generating a synchronous busy signal starting from a first synchronizing clock after the inverted output of the busy signal generating flip-flop is rendered active, and a buffer circuit having an input connected to receive the synchronous busy signal and an output connected to the data transfer terminal, the output of the buffer circuit assuming a high impedance condition when the synchronous busy signal is inactive and a low level condition when the synchronous busy signal is active so that when the data transfer terminal is connected to a pulled-up data transfer line, the data transfer line is selectively brought either into a low level or into a high level in accordance with the output condition of the buffer circuit.

Claim 16

A data processor claimed in Claim 9 wherein the transfer inhibit signal generating means includes a flip-­flop having a set input connected to receive the reception end signal and a reset input connected to receive the transfer acknowledge signal, the flip-flop also having an inverted output generating a busy signal which is rendered active when the reception end signal becomes active and is rendered inactive when the transfer acknowledge signal becomes active.

Claim 17

A data processor claimed in Claim 11 wherein the inverted output of the flip-flop is connected to a busy signal terminals independent of the data transfer terminal.

Claim 18

A data processor claimed in Claim 11 wherein the data receiving means is adapted to generate a synchronizing clock after the predetermined length of data has been received, and further including a synchronizing flip-flop receiving the inverted output of the busy signal generating flip-flop and the synchronizing clock for generating a synchronous busy signal starting from a first synchronizing clock after the inverted output of the busy signal generating flip-flop is rendered active, and a buffer circuit having an input connected to receive the synchronous busy signal and an output connected to the data transfer terminal, the output of the buffer circuit assuming a high impedance condition when the sysnchronous busy signal is inactive and a low level condition when the synchronous busy signal is active so that when the data transfer terminal is connected to a pulled-up data transfer line, the data transfer line is selectively brought either into a low level or into a high level in accordance with the output condition of the buffer circuit.

Claim 19

A data transfer system including a first data processor and a second data processor coupled through a data transfer line connected through a pull-up resistor to a voltage supply and through a clock line, the first data processor comprising a data processing means for supplying a predetermined length of data to be transferred and generating a transfer start signal, a data transferring means receiving the predetermined length of data to be transferred from the data processing means for transferring the same data through a buffer means to a data transferring terminal connected to the data transfer line, the data transferring means supplying a synchronous clock to a clock transfer terminal connected to the clock line, means connected to the data transferring terminal for detecting a transfer inhibit signal, means receiving the transfer start signal from the data processing means for temporarily holding the same transfer start signal, and transfer control means associated to the data transferring means for causing the data transferring means to stop the transfer of data during the period the transfer inhibiting signal is active and allowing the data transferring unit to start the transfer of data at least when the transfer inhibiting signal becomes inactive after the transfer start signal is generated, and the second data processor comprising a data receiving means connected to a data receiving terminal connected to the data transfer line for receiving the predetermined length of data through the data transfer line, the data receiving means being also connected to a clock receiving terminal connected to the clock line, a data processing maens coupled to the receiving means for processing the received data and generating a transfer acknowledge signal when it has completed the processing of the received data, and a busy signal generator for generating the above mentioned busy signal through a buffer circuit to data receiving terminal in response to completion of reception of the predetermined length of data and making the busy signal inactive when the transfer acknowledge signal is generated.

Claim 20

A data transfer system including a first data processor and a second data processor coupled through a data transfer line connected through a pull-up resistor to a voltage supply and through a clock line, the first data processor comprising a data processing means for supplying a predetermined length of data to be transferred and generating a transfer start signal, a data transferring means receiving the predetermined length of data to be transferred from the data processing means for transferring the same data through a buffer means to a data transferring terminal connected to the data transfer line, the data transferring means supplying a synchronous clock to a clock transfer terminal connected to the clock line, means connected to the data transferring terminal for detecting a transfer inhibit signal, means receiving the transfer start signal from the data processing means for temporarily holding the same transfer start signal, and transfer control means associated to the data transferring means for causing the data transferring means to stop the transfer of data during the period the transfer inhibiting signal is active and allowing the data transferring unit to start the transfer of data at least when the transfer inhibiting signal becomes inactive after the transfer start signal is generated, and the second data processor comprising a data receiving means connected to a data receiving terminal connected to the data transfer line for receiving the predetermined length of data through the data transfer line, the data receiving means being also connected to a clock receiving terminal connected to the clock line, a data processing maens coupled to the receiving means for processing the received data and generating a transfer acknowledge signal when it has completed the processing of the received data, and a busy signal generator for generating the above mentioned busy signal through a buffer circuit to data receiving terminal in response to completion of reception of the predetermined length of data and making the busy signal inactive when the transfer acknowledge signal is generated.