Parallel computer with distributed shared memories and distributed task activating circuits

Claim 2

A parallel computer, comprising: (a) a plurality of element processors (100) each for exe­cuting task programs assigned thereto among a plurality of task programs to be executed by said parallel computer; and (b) network means (7) connected to said element pro­cessors for enabling signal transfer therebetween; each element processor (100) including: (a1) first memory means (2) for holding data and instruc­tions included in a group of task programs assigned thereto; (a2) execution means connected to said first memory means for fetching and executing instructions held thereby in such a manner that instructions included in a task program under ex­ecution are sequentially executed, including first means (25A) responsive to a predetermined instruction included in the task program under execution for providing said network means with a control token signal, a processor indication signal, indica­tive of an element processor to which a succeeding task pro­gram is assigned which is allowed to be executed after execu­tion of the task program under execution and a task program indication signal indicative of the succeeding task program, so as to request said network means to send the control token signal and the task program indication signal to the element processor indicated by the element processor indication sig­nal; (a3) second memory means (32) for holding predetermined total numbers of control token signals which respective ones of the group of task programs require to receive before being executed; and (a4) control means connected to said network means, said second memory means and said execution means and responsive to control token signals and task program indication signals pro­vided from said network means for detecting which one of the group of task programs is allowed to be executed depending upon the total numbers of control token signals predetermined for and total numbers of control token signals already re­ceived for respective task programs and for informing said ex­ecution means of the detected are task program so as to be ex­ecuted next.

Claim 3

A parallel computer according to claim 1, wherein said second memory means (32) further holds a plurality of number signals each varying depending upon a number of control sig­nals which are already received for a corresponding one of the group of task programs; and wherein said control means includes means responding to the reception of a control token signal and a task program identification signal for renewing one of the number signals corresponding to a task program identified by the received task number identification signal and for detecting whether or not the number of all control token signals already received for the task program is equal to the total number of control token signals predetermined for the task number.

Claim 4

A parallel computer according to claim 2, wherein each number signal indicates the difference between a total number of control token signals predetermined for a corresponding task program and a total number of control token signals already received for the corresponding task program.

Claim 5

A parallel computer according to claim 1, wherein said second memory means (32) further holds a plurality of instruc­tion address signals each indicative of an address of said first memory means for a starting instruction of a correspon­ding task program; and wherein said control means includes means for informing said execution means of one of the in­struction address signals corresponding to the one detected task program.

Claim 6

A parallel computer according to claim 1, wherein said second memory means (132) further holds a plurality of para­meter address signals each indicative of a storage location within said first memory means which holds a signal required for execution of a corresponding task program; and wherein said control means (30A) includes means for transferring to said execution means one of the plurality of parameter address signals corresponding to the one detected task program.

Claim 7

A parallel computer according to claim 1, wherein said second memory means (32) further holds a sequence signal in­dicating an order of execution of a plurality of task programs which are detected by said control means as being executable; and wherein said control means includes means for renewing the sequence signal when said control means detects that another task program has fallen into an executable state, so that the other task program is executed after execution of task programs which were previously detected as being execu­table .

Claim 8

A parallel computer according to claim 1, wherein said second memory means (32) has a plurality of storage locations each provided for a corresponding one of the group of task programs, each storage location having first to fifth fields, the first field holding the total number of control token sig­nals predetermined for the corresponding task program, the second field holding the total number of control signals which are not yet received for the corresponding task program, the third field holding an instruction address indicative of a storage location within said first memory means (2) which holds a starting instruction included in the corresponding task program and the fourth field holding a parameter address indicative of a storage location within said first memory means which holds a parameter signal required for execution of the corresponding task program; and wherein said control means includes first and second re­gisters (35; 36) and means (30; 33) responsive to the recep­tion of each pair of pairs of a control token signal and a task program identification signal for decrementing a content of the second field of a storage location of said second memo­ry means corresponding to a task program identified by the re­ceived task program identification signal, for detecting exe­cutability of the corresponding task program based upon whether or not a content of the second field of the storage location after the decrementation is zero, for writing an address of the storage location into the first and second re­gisters when the corresponding task program is detected as being executable and there is no other task program which is already detected as being executable, for writing the address of the storage location into the second register and into the fifth field of a storage location within said second memory means for another task program when the corresponding task program is detected as being executable and the other task program has been most recently detected as being executable prior to the detection of executability of the corresponding task program, and responsive to an end of execution of a task program under execution by said execution means for providing said execution means with contents of the third and fourth fields of a storage location within said second memory means pointed by a pointer address held in the fifth field of a storage location within said second memory means corresponding to the task program under execution, so as to enable said exe­cution means to execute a task program corresponding to the pointed storage location.

Claim 9

A parallel computer according to claim 1, wherein said execution means includes: third memory means (20) for holding pairs of a succeeding task program indication signal and an element processor indi­cation signal, the former indicating one of a plurality of succeeding task programs which are allowed to be executed after execution of the task program under execution and the latter indicating an element processor to which the one suc­ceeding task program is assigned; and control means (42, 23) responsive to the predetermined instruction for generating the control token signal, for reading the pairs from said third memory means and for pro­viding said network means with each of the pairs each with the control token signal.

Claim 10

A parallel computer according to claim 8, wherein said third memory means (20) includes a plurality of storage lo­cations, a partial number of which each holds one of the pairs, each of the partial number of storage locations further holding a pointer indicative of another storage location with­in the partial number of storage locations; and wherein said control means includes means responsive to the predetermined instruction for generating an address of a first one of the partial number of storage locations to read signals held therein and for sequentially accessing remaining ones of the partial number of storage locations each by means of a pointer signal read out from an already accessed storage location.

Claim 11

A parallel computer comprised of a plurality of element processors (100) operable in parallel and each connected to each other for communication therebetween, each element processor comprising: (a) first memory means (2) for holding data; (b) execution means connected to said first memory means for executing instructions assigned to each element pro­cessor including memory access means responsive to memory write or memory read instructions each designating a storage location of said first memory means for accessing the storage location to write a datum therein or to read a datum there­from; (c) send means connected to said execution means and other element processors and responsive to execution of one of the memory write instructions by said execution means for detecting whether or not a first storage location designated thereby is a predetermined one and responsive to the detection for sending a datum written into the first storage location as a result of execution of the one memory write instruction to a predetermined one of the other element processors which is to execute an instruction which makes use of the datum.

Claim 12

A parallel computer comprised of a plurality of element processors (100) operable in parallel and each connected to each other for communication therebetween, each element processor comprising: (a) first memory means (2) for holding data; (b) execution means connected to said first memory means for executing instructions assigned to each element pro­cessor including memory access means responsive to memory write or memory read instructions each designating a storage location of said first memory means for accessing the storage location to write a datum therein or to read a datum there­from; (c) send means connected to said execution means and other element processors and responsive to execution of one of the memory write instructions by said execution means for detecting whether or not a first storage location designated thereby is a predetermined one and responsive to the detection for sending a datum written into the first storage location as a result of execution of the one memory write instruction to a predetermined one of the other element processors which is to execute an instruction which makes use of the datum.

Claim 13

A parallel computer according to claim 10, wherein said send means includes means for sending, together with the datum, an address corresponding to a second storage location of said first memory means included in said one other el­ ement processor.

Claim 14

A parallel computer according to claim 11, wherein each element processor further includes means responsive to the re­ception of a datum and an address provided from another el­ement processor for writing the received datum into a storage location corresponding to the received address within said first memory means within each element processor.