Patent EP0315705A1 successfully refreshed from Google Patents.
EP0258042A2
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EP
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Phase locked loop circuit with quickly recoverable stability
Assignee: Panasonic Holdings Corp
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Filing: 1987-08-25
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Granted: —
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Expires: 2007-08-25
Abstract
Abstract A PLL circuit for a phase comparator, a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider. A first control circuit is responsive to a discontinuous phase change of a reference signal of the PLL circuit for inhibiting the operation of the phase comparator or disconnecting the LPF from the phase comparator during a predetermined period so that the discontinuous phase change information is not transmitted through the LPF to the VCO. At the same time, a second control circuit resets the frequency divider by a pulse of the reference signal after the discontinuous phase change or applies a voltage corresponding to the discontinuous phase change to the VCO so that the output signal of the frequency divider is locked in phase to the reference signal after the discontinuous phase change. With the cooperation of the first and second control circuits, the PLL circuit quickly recovers its stable state after the discontinuous phase change of the reference signal.
Inventors
- 👤 Masahiro Honjo
- 👤 Atsuo Ochi
- 👤 Akihiro Takeuchi
- 👤 Shinichi Aki
- 👤 Yukio Nakagawa
- 👤 Masaaki Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:42
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/199; H04N5/76; H04N5/91; H04N5/93; H04N5/95; H04N5/956
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
166 words
A phase locked loop circuit comprising: a voltage-controlled oscillator oscillating at a frequency corresponding to a voltage applied thereto; a frequency divider for dividing the oscillation frequency of the voltage-controlled oscillator; a phase comparator for comparing phases of a reference signal inputted to the PLL circuit and an output signal of the frequency divider; a low-pass filter for converting a phase comparison result of the phase comparator to a voltage for controlling the voltage-controlled oscillator; first control means responsive to a discontinuous phase change of the reference signal for preventing a phase change of the reference signal from being transmitted through the low-pass filter to the voltage-controlled oscillator during a predetermined period; and second control means responsive to the discontinuous phase change of the reference signal for forcedly pulling-in the phase of the PLL circuit so that the phase of the output signal of the frequency divider is locked to a new phase of the reference signal after the discontinuous phase change during a predetermined period.
Claim 2
Dependent Claim
166 words
A phase locked loop circuit comprising: a voltage-controlled oscillator oscillating at a frequency corresponding to a voltage applied thereto; a frequency divider for dividing the oscillation frequency of the voltage-controlled oscillator; a phase comparator for comparing phases of a reference signal inputted to the PLL circuit and an output signal of the frequency divider; a low-pass filter for converting a phase comparison result of the phase comparator to a voltage for controlling the voltage-controlled oscillator; first control means responsive to a discontinuous phase change of the reference signal for preventing a phase change of the reference signal from being transmitted through the low-pass filter to the voltage-controlled oscillator during a predetermined period; and second control means responsive to the discontinuous phase change of the reference signal for forcedly pulling-in the phase of the PLL circuit so that the phase of the output signal of the frequency divider is locked to a new phase of the reference signal after the discontinuous phase change during a predetermined period.
Claim 3
Dependent Claim
143 words
A phase locked loop circuit according to claim 1, wherein the first control means comprises a first pulse generator responsive to the discontinuous phase change of the reference signal for generating a first pulse having a predetermined duration for inhibiting the operation of the phase comparator during the predetermined duration of the first pulse, and wherein the second control means comprises: a second pulse generator responsive to the discontinuous phase change of the reference signal for generating a second pulse having a predetermined duration; and a switch responsive to the second pulse for applying a pulse of the reference signal after the discontinuous phase change to the frequency divider during the predetermined duration of the second pulse to reset the frequency divider, thereby forcedly locking the phase of the output signal of the frequency divider to the new phase of the reference signal.
Claim 4
Dependent Claim
191 words
A phase locked loop circuit according to claim 1, wherein the first control means comprises a first pulse generator responsive to the discontinuous phase change of the reference signal for generating a first pulse having a predetermined duration, and a first switch responsive to the first pulse for disconnecting the low-pass filter from the phase comparator during the predetermined duration of the first pulse, and wherein the second control means comprises: a second pulse generator responsive to the discontinuous phase change of the reference signal for generating a second pulse having a predetermined duration; a voltage generator for generating a voltage signal corresponding to the discontinuous phase change of the reference signal; a second switch responsive to the second pusle for passing the voltage signal generated by the voltage generator during the predetermined duration of the second pulse; and a voltage adder for adding output voltages from the low-pass filter and the second switch and applying an added voltage to the voltage-controlled oscillator to forcedly change the oscillation frequency so that the phase of the output signal of the frequency divider becomes locked to the new phase of the reference signal.
References Cited (Backward Citations)
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