EP0255186A2
Expired / Lapsed
EP
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System and method for parallel processing with mostly functional languages
Assignee: Egendorf Andrew
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Filing: 1987-07-29
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Granted: —
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Expires: 2007-07-29
Abstract
Abstract A parallel processing system is receptive of a program and has at least two processors (1) connected in parallel to a shared main memory (6, 7). Each processor (1) executes instructions of the program which includes side effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory. The program is compiling into a series of independent instruction blocks including predominantly functional instructions and terminating in a side-effecting instruction and the processors execute the blocks in parallel.
Inventors
- 👤 Thomas F. Knight, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 19:14
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833; G06F8/00; G06F8/40; G06F8/41; G06F8/45
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
96 words
In a parallel processing system receptive of a program and having at least two processors connected in parallel to a shared main memory, wherein each processor executes instructions of a program which includes side effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory or operate only on internal processor registers, the improvement comprising: means for compiling a program into a series of independent instruction blocks including predominantly functional instructions and terminating in a side-effecting instruction; and wherein the processors execute the blocks in parallel.
Claim 2
Dependent Claim
96 words
In a parallel processing system receptive of a program and having at least two processors connected in parallel to a shared main memory, wherein each processor executes instructions of a program which includes side effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory or operate only on internal processor registers, the improvement comprising: means for compiling a program into a series of independent instruction blocks including predominantly functional instructions and terminating in a side-effecting instruction; and wherein the processors execute the blocks in parallel.
Claim 3
Dependent Claim
34 words
The system according to claim 1, further comprising for each processor, means for maintaining a dependency list of all locations in main memory which have been referenced during the execution of a block therein.
Claim 4
Dependent Claim
112 words
The system according to claim 2, further comprising first cache means associated with each processor for temporarily storing the location and contents of each location in main memory to be side effected by the execution of the block therein and means for confirming each block in the order of the blocks as specified in the program wherein the validity of the contents of the first cache means are approved comprising means for comparing the dependency list of the block to be confirmed with the locations side effected by already confirmed blocks to detect a match and means for aborting the execution of the block to be confirmed if there is a match.
Claim 5
Dependent Claim
29 words
The system according to claim 3, wherein the confirming means comprises a block counter and means for incrementing the block counter to indicate the next block to be confirmed.
Claim 6
Dependent Claim
82 words
The system according to claim 3, wherein the means for maintaining a dependency list comprises second cache means associated with each processor for temporarily storing each location and contents of main memory referenced by a block being executed in the processor and wherein the confirming means comprises means for updating the contents of the second cache means upon the aborting of a block and for effecting the reexecution of an aborted block with the side effected location from an already confirmed block.
Claim 7
Dependent Claim
21 words
The system according to claim 5, wherein the first and second cache means each comprises a fully associative content addressable memory.
Claim 8
Dependent Claim
54 words
The system according to claim 5, wherein the second cache means comprises an addressable random access memory for storing dependency information of main memory locations and hash table means receptive of said addresses of the main memory locations for hashing them into a reduced member of address bits for addressing the random access memory.
Claim 9
Dependent Claim
30 words
The system according to claim 2, wherein the means for maintaining a dependency list includes means for selectively referencing locations in main memory without adding same to the dependency list.
Claim 10
Dependent Claim
81 words
In a method for executing a program in at least two processors connected in parallel to a shared main memory, wherein the program includes side effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory, the improvement comprising: compiling the program into a series of independent instruction blocks including predominantly functional instructions and terminating in a side-effecting instruction, applying the blocks to the processors and executing the blocks in parallel.
Claim 11
Dependent Claim
81 words
In a method for executing a program in at least two processors connected in parallel to a shared main memory, wherein the program includes side effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory, the improvement comprising: compiling the program into a series of independent instruction blocks including predominantly functional instructions and terminating in a side-effecting instruction, applying the blocks to the processors and executing the blocks in parallel.
Claim 12
Dependent Claim
36 words
The method according to claim 9, wherein the step of executing comprises maintaining a dependency list for each processor of all locations in main memory which have been referenced during the execution of a block therein.
Claim 13
Dependent Claim
90 words
The method according to claim 10, wherein the step of executing further comprises for each processor temporarily storing the location and contents of each location in main memory to be side effected by the execution of the block therein and confirming each block in the order of the blocks as specified in the program to approve the validity of the stored contents by comparing the dependency list of the block to be confirmed with the locations which have been side effected by the already confirmed blocks to detect a match.
Claim 14
Dependent Claim
24 words
The method according to claim 11, wherein the step of executing further comprises aborting the execution of a block when there is a match.
Claim 15
Dependent Claim
51 words
The method according to claim 12, wherein the step of maintaining a dependency list comprises temporarily storing for each processor each location and contents of main memory referenced by the block being executed therein and wherein the step of executing further comprises reexecuting an aborted block from an already confirmed block.
Claim 16
Dependent Claim
44 words
The method according to claim 13, wherein the step of temporarily storing the referenced locations comprises hashing each location address into a hashed address having a reduced number of address bits and storing dependency information at the hashed address in a random access memory.
Claim 17
Dependent Claim
24 words
The method according to claim 10, where in the step of maintaining a dependency list includes selectively omitting referenced locations from the dependency list.
References Cited (Backward Citations)
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