Method and apparatus for multi-gradation display

Claim 2

A multi-gradation display method by which display signals formed by picture element signals, each indicating any one of the levels of N gradations (where N is an integer equal to or greater than 3), are displayed on a display panel in which each picture element provides a two-gradation display, wherein a binary signal is supplied to each picture element (N - l) times for displaying one frame, and the binary signal is given one of two values a number of times corresponding to the value of the input picture element signal, out of (N - l) times, thereby providing a multi-gradation display in one frame.

Claim 5

A multi-gradation display apparatus which is provided with a first dot clock generator (22) for generating a first dot clock (DCK, DCK₂), a picture element counter (25) for frequency dividing the first dot clock (DCK, DCK₂) down to l/n to obtain a row clock (HCK), a row counter (27) for frequency dividing the row clock (HCK) down to l/ℓ to obtain a field clock (VCK), a dot shift register (3l) of n shift stages supplied with the first dot clock (DCK, DCK₂) as a shift clock from the first dot clock generator (22), a column latch/drive circuit (26) for latching the contents of the dot shift register (3l) by the row clock (HCK) from the picture element counter (25); a row shift register/drive circuit (28) supplied with the field clock (VCK) as a data input from the row counter (27) and the row clock (HCK) as a shift clock from the picture element counter (25), and a display panel (32, 54) in which picture elements are arranged in the form of a matrix with ℓ rows and n columns, the picture elements on the n columns are connected to n column drive lines respectively corresponding thereto, the picture elements on the ℓ rows are connected to ℓ row drive lines respectively corresponding thereto, the picture elements are each driven by inputs to the column and row drive lines connected thereto to provide a display accordingly, the n column drive lines are respectivley connected to n outputs of the column latch/drive circuit (26), and the ℓ row drive lines are respectively connected to ℓ outputs of the row shift register/drive circuit (28), characterized by: a frame memory (2l) in which ℓ × n picture element signals of one frame are stored as display signals each of the picture element signals having M bits (where 2 M is greater than or equal to N which is an integer greater than or equal to 3) indicating any one of the levels of N gradations; a readout address counter (23) which counts the first dot clock (DCK, DCK₂) from the first dot clock generator (22) and supplies the count value as an address to the frame memory (2l) to read it out and is reset by the field clock (FCK) from the row counter (27); a field counter (29) for counting the field clock (FCK) from the row counter (27); and an M-bit comparator (24) which compares the count value CN of the field counter (29) and the level value P of each picture element signal read out of the frame memory (2l) and outputs a binary signal of one of its two values when CN > P and a binary signal of the other value when CN ≦ P, the binary signal output being applied as a data input to the dot shift register (3l).

Claim 6

A multi-gradation display apparatus which is provided with a first dot clock generator (22) for generating a first dot clock (DCK, DCK₂), a picture element counter (25) for frequency dividing the first dot clock (DCK, DCK₂) down to l/n to obtain a row clock (HCK), a row counter (27) for frequency dividing the row clock (HCK) down to l/ℓ to obtain a field clock (VCK), a dot shift register (3l) of n shift stages supplied with the first dot clock (DCK, DCK₂) as a shift clock from the first dot clock generator (22), a column latch/drive circuit (26) for latching the contents of the dot shift register (3l) by the row clock (HCK) from the picture element counter (25); a row shift register/drive circuit (28) supplied with the field clock (VCK) as a data input from the row counter (27) and the row clock (HCK) as a shift clock from the picture element counter (25), and a display panel (32, 54) in which picture elements are arranged in the form of a matrix with ℓ rows and n columns, the picture elements on the n columns are connected to n column drive lines respectively corresponding thereto, the picture elements on the ℓ rows are connected to ℓ row drive lines respectively corresponding thereto, the picture elements are each driven by inputs to the column and row drive lines connected thereto to provide a display accordingly, the n column drive lines are respectivley connected to n outputs of the column latch/drive circuit (26), and the ℓ row drive lines are respectively connected to ℓ outputs of the row shift register/drive circuit (28), characterized by: a frame memory (2l) in which ℓ × n picture element signals of one frame are stored as display signals each of the picture element signals having M bits (where 2 M is greater than or equal to N which is an integer greater than or equal to 3) indicating any one of the levels of N gradations; a readout address counter (23) which counts the first dot clock (DCK, DCK₂) from the first dot clock generator (22) and supplies the count value as an address to the frame memory (2l) to read it out and is reset by the field clock (FCK) from the row counter (27); a field counter (29) for counting the field clock (FCK) from the row counter (27); and an M-bit comparator (24) which compares the count value CN of the field counter (29) and the level value P of each picture element signal read out of the frame memory (2l) and outputs a binary signal of one of its two values when CN > P and a binary signal of the other value when CN ≦ P, the binary signal output being applied as a data input to the dot shift register (3l).

Claim 7

The apparatus of claim 4, wherein the frame memory (2l) comprises first and second frame memories (2la, 2lb), each display signal is a TV signal, a second dot clock (DCK₁) generated by a second dot clock generator (56) in synchronism with the picture element signals is counted by a write address counter (48), the count value of the write address counter (48) is applied as a write address to one of the first and second frame memories (2la, 2lb) via an address selector (49), the count value of the readout address counter (23) is applied as a readout address to the other of the first and second frame memories (2lb, 2la) via the address selector (49), the TV signal is converted by an AD converter (44) into an M-bit digital value for each picture element signal, the converted digital value is applied as a write data via a first selector (5l) to one of the first and second frame memories (2la, 2lb) which is being supplied with the write address; the output read out of one of the first and second frame memories (2la, 2lb) which is being supplied with the readout address is provided via a second selector (52) to the M-bit comparator (24); the second dot clock generator (56) and the write address counter (48) are synchronously controlled by a vertical synchronizing signal of the TV signal; the vertical synchronizing signal is frequency divided by a flip-flop (55) down to l/2, the first and second selectors (5l, 52) and the address selector (49) are switched under control of the frequency-divided output of the flip-flop (55); and the frequency of the second dot clock (DCK₁) of the second dot clock generator (56) is selected about (N - l) times higher than the frequency of the first dot clock (DCK₂, DCK) of the first dot clock generator (22).

Claim 8

The apparatus of claim 5, wherein the TV signal is a color TV signal; a third selector (43) is controlled by a color select control circuit (45) which operates on a clock of a frequency three times higher than that of the color signals each composed of red, green and blue color pixel signals; the red, green and blue color pixel signals in the color TV signal are selectively applied via the third selector (43) to the AD converter (44); every three of the n outputs of the column latch drive circuit (26) correspond to the red, green and blue color pixel signals; and every three picture elements in the display panel (54) are formed by red, green and blue color pixels.

Claim 9

The apparatus of claim 4, wherein the display panel (32, 54) is a liquid crystal display panel.