Semiconductor memory system

Claim 2

A semiconductor memory system comprising a) a memory cell including a memory transistor (Q M ) which has a first threshold voltage (V TM (E)) higher than a predetermined reference level (V GRD ) when the memory transistor is in a state storing one of a logic "1" bit of data and a logic "0" bit of data and a second threshold voltage (V TM (W)) lower than said reference level when said memory transistor is in a state storing the other of said logic "1" bit of data and said logic "0" bit of data; b) a control circuit (32) comprising (b-1) readout voltage generating means (Q 3 , Q 4 , Q 5 ) operative to produce a readout voltage (V R2 = V T ) intervening between.said reference level and said first threshold voltage, said memory transistor being responsive to said readout voltage for having a first state if the memory transistor has said first threshold voltage and a second state if the memory transistor has said second threshold voltage; and c) readout means (22) responsive to each of said first state and said second state of said memory transistor for reading the logic "1" bit of data or the logic "0" bit of data stored therein.

Claim 3

A semiconductor memory system as set forth in claim 1, in which said control circuit further comprises write voltage generating means operative to produce a write voltage of a predetermined level for producing one of said first state and said second state in said memory transistor to store said logic "1" bit of data into the transistor, and erase voltage generating means operative to produce an erase voltage of another predetermined level for producing the other of said first state and said second state in said memory transistor to store said logic "0" bit of data into the transistor.

Claim 4

A semiconductor memory system as set forth in claim 2, in which said memory transistor is of the non-volatile type and in which said gate control circuit has a circuit output terminal and is associated with a first voltage supply terminal for a constant supply voltage, a second voltage supply terminal for a predetermined write-erase voltage higher than said supply voltage, and control signal generating means operative to produce write, erase and readout control signals each having two logic states and in which said erase voltage generating means and said write voltage generating means comprises first and second transistors, respectively, and said readout voltage generating means comprises third, fourth and fifth transistors, each of said first, second, third and fourth transistors having a control terminal and current input and output terminals, wherein said first transistor has its input terminal connected to said second voltage supply terminal, its control terminal arranged to be responsive to said erase control signal and its output terminal connected to said circuit output terminal, the first transistor being conductive in response to the erase control signal of one of said logic states, said second transistor has its input terminal connected to said circuit output terminal and its control terminal arranged to be responsive to said write control signal, the second transistor being conductive in response to the write control signal of one of said logic states, said third transistor has its input terminal connected to said first voltage supply terminal, its control terminal arranged to be responsive to said readout control signal and its output terminal connected to said circuit output terminal, the third transistor being conductive in response to the readout control signal of one of said logic states, said fourth transistor has its control terminal arranged to be responsive to said readout control signal, the fourth transistor being conductive in response to the readout control signal of one of said logic states, and said fifth transistor has its control terminal and input terminal coupled together, one of said fourth and fifth transistors having its input terminal connected to said circuit output terminal and its output terminal connected to the control terminal and input terminal of the other of said fourth and fifth transistors, the other of the fourth and fifth transistors being grounded.

Claim 5

A semiconductor memory system as set forth in claim 3, in which said fourth transistor has its input terminal connected to said circuit output terminal and said fifth transistor has its control terminal and input terminal jointly connected to the output terminal of said fourth transistor and has its output terminal grounded.

Claim 6

A semiconductor memory system as set forth in claim 3, in which said fifth transistor has its control terminal and input terminal jointly connected to said circuit output terminal and said fourth transistor has its input terminal connected to the output terminal of said fifth transistor and has its output terminal grounded.

Claim 7

A semiconductor memory system as set forth in claim 3, in which each of said first, second, third and fourth transistors consists of a field-effect transistor having its gate, drain and source provided by said control terminal, said input terminal and said output terminal, respectively, of each of the first to fifth transistors.

Claim 8

A semiconductor memory system as set forth in claim 6, in which each of said first, second, third and fourth transistors consists of an n-channel field-effect transistor.

Claim 9

A semiconductor memory system as set forth in claim 7, in which each of said first, second and fourth transistors consists of an n-channel field-effect transistor and said third transistor consists of a p-channel field-effect transistor.

Claim 10

A semiconductor memory system including a non-volatile semiconductor memory element having a floating gate, comprising a) a voltage step-up circuit operative to produce a high voltage higher than a supply voltage during erase mode of operation, b) a first field-effect transistor which has its drain connected to a first node at which is established a high voltage which is enough to erase information in said memory element during erase mode of operation and its gate connected to the output terminal of said voltage step-up circuit, said first field-effect transistor being in conduction state during erase mode of operation, c) a second field-effect transistor which is connected between the source of said first field-effect-transistor and which is controlled to be in conduction state during write mode of operation, d) a third field-effect transistor having its drain connected to a second node between said supply voltage and its source connected to the source of said first field-effect transistor and the drain of said second field-effect transistor, said third field-effect transistor being in conduction state during readout mode of operation, e) a fourth field-effect transistor controlled to be in conduction state during readout mode of operation, f) a fifth field-effect transistor serially connected to said fourth field-effect transistor and having its gate and drain connected together, and g) a circuit block connected between said second node and ground, said memory element being connected to said second node.

Claim 11

A semiconductor memory system including a non-volatile semiconductor memory element having a floating gate, comprising a) a voltage step-up circuit operative to produce a high voltage higher than a supply voltage during erase mode of operation, b) a first field-effect transistor which has its drain connected to a first node at which is established a high voltage which is enough to erase information in said memory element during erase mode of operation and its gate connected to the output terminal of said voltage step-up circuit, said first field-effect transistor being in conduction state during erase mode of operation, c) a second field-effect transistor which is connected between the source of said first field-effect-transistor and which is controlled to be in conduction state during write mode of operation, d) a third field-effect transistor having its drain connected to a second node between said supply voltage and its source connected to the source of said first field-effect transistor and the drain of said second field-effect transistor, said third field-effect transistor being in conduction state during readout mode of operation, e) a fourth field-effect transistor controlled to be in conduction state during readout mode of operation, f) a fifth field-effect transistor serially connected to said fourth field-effect transistor and having its gate and drain connected together, and g) a circuit block connected between said second node and ground, said memory element being connected to said second node.