High speed interconnect unit for digital data processing system

Claim 1

An interconnect unit for connection to a system bus in a digital data processing system including a memory for storing information and.a processor means for controlling the system, said interconnect unit transferring information between the memory over said system bus and an external device over an external bus, said external bus including bidirectional information transfer lines for transferring informa- t ion signals, antiparallel unidirectional direction control lines for transferring direction control signals and antiparallel unidirectional synchronization control lines for transferring synchronization signals, in response to commands therefor from the processor means, said interconnect unit including: A. system transfer means for connected to said system bus for transferring information to or from said memory, B. external device transfer means including means for connection to said external bus for transmitting and receiving information over said external bus, and including: i. information transfer means connucted to said system transfer means and for connection to said information transfer lines for transferring information between said system transfer means and said information transfer lines; ii. direction control means for connection to said direction control lines for transmitting a signal on one of said lines and receiving a signal on the other of said lines identifying the direction of transfer of information over said information transfer lines, and iii. synchronization control means for connection to said synchronization control lines for transmitting a signal on one of said lines and receiving a signal on the other of said lines to synchronize the transfer of information over said information transfer lines, and C. control means connected to said information transfer means, said direction control means and said synchronization control means for controlling the operation of the respective means in transferring information over said information transfer lines, said control means including: i. means for enabling said direction control means to transmit and receive the direction control signals over the respective direction control lines to identify the direction of transfer, ii. means for enabling said information transfer means to transmit or receive information signals over said information transfer lines responsive to the condition of said direction control signals, and iii. means for enabling said synchronization control means to transmit a synchronization control signal to identify: I. when information signals are being transferred over said information transfer lines when said direction control signals indicate that information is being transferred to said external device to enable said external device to receive said information signals, or II. when information signals have been received from said information transfer lines when said direction control signals indicate that information is being transferred from said external device.