EP0253095A2
Expired / Lapsed
EP
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Memory interface system
Assignee: Texas Instruments Inc
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Filing: 1981-06-23
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Granted: —
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Expires: 2001-06-23
Abstract
Abstract A memory system for coupling memory circuits (650) to controller circuits (620) in a data processing system. The controller circuit (620) transmits command, data and address signals via a single bus (622) and is responsive to selected data and address signals on the bus (622). The memory circuits (650) selectively transfer data to and from the controller circuit (620) In response to selected command and address signals. A command decode circuit (632) in each memory circuit (650) preferably includes means for incrementing the program counter (634) after each memory operation in response to selected command signals, thereby enabling a number of sequential memory operations in response to a single command. At least one memory circuit (650) is preferably a plug-in read-write memory module having a power switching circuit (648) for providing continuous power from the main power bus (628) of the data processing system or a battery (646) housed within the plug-in module.
Inventors
- 👤 Stephen P. Hamilton
- 👤 Arthur C. Hunter
- 👤 Kenneth A. Lies
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F1/00; G06F1/26; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G11; G11C; G11C5/00; G11C5/14; G11C5/141
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
121 words
A memory interface system comprising: processor means for transmitting a command signal on a common bus including means for selectively outputting an address and data signal onto said common bus responsive to said command signal, only one of said command, address, and data signal outputs being on said common bus at any one time, in a command originated sequence; and memory means for storing and retrieving said data signal, coupled to said common bus, including command detect means for outputting a command detect signal in response to said command signal, and decode means coupled to said command detect means for activating said memory means to store or retrieve said data signal responsive to said command signal and-to said command detect signal.
Claim 2
Dependent Claim
121 words
A memory interface system comprising: processor means for transmitting a command signal on a common bus including means for selectively outputting an address and data signal onto said common bus responsive to said command signal, only one of said command, address, and data signal outputs being on said common bus at any one time, in a command originated sequence; and memory means for storing and retrieving said data signal, coupled to said common bus, including command detect means for outputting a command detect signal in response to said command signal, and decode means coupled to said command detect means for activating said memory means to store or retrieve said data signal responsive to said command signal and-to said command detect signal.
Claim 3
Dependent Claim
37 words
The memory interface system as in Claim 1 wherein said command detect means includes means for outputting said command detect signal in response to detecting a command commencement transition of said command signal on said common bus.
Claim 4
Dependent Claim
43 words
3, The system as in Claim 1 further comprising cycle sequencing means, within said decode means, for selectively coupling one of a data bus, an address bus and a control bus within said memory means to said common-bus responsive to said command signal.
Claim 5
Dependent Claim
33 words
The system as in Claim 1 wherein said decode means includes means for selectively outputting stored data from said memory means onto said common bus in response to one of said command signals.
Claim 6
Dependent Claim
32 words
The system as in Claim 1 wherein the said decode means includes means for outputting stored data from multiple locations within said memory means responsive to said one of said command signals.
Claim 7
Dependent Claim
33 words
The system as in Claim 1 wherein the said decode means includes means for selectively storing said data signal in said memory means in response to a second one of said command signals.
Claim 8
Dependent Claim
39 words
The system as in Claim 6 wherein the decode means further includes means for storing sequentially received ones of said data signals in multiple locations within the memory means in response to said second one of said command signals.
Claim 9
Dependent Claim
16 words
The system as in Claim 1 wherein said memory means is comprised of a read-only memory.
Claim 10
Dependent Claim
18 words
The system as in Claim 1 or 2 wherein said memory means is comprised of a read-write memory.
Claim 11
Dependent Claim
18 words
The system as in Claim 1 wherein said memory means is comprised of separate read-only and read-write memories.
Claim 12
Dependent Claim
206 words
A data processing system comprising: bus means for providing transfer paths: processor means coupled to the bus means for selectively transmitting or receiving address, data and command group signals via the bus means, only one of said signals being transferred on the bus means at any given time; memory means coupled to said bus means for selectively storing and outputting data in one of a set of memory cycles responsive to said command signals; first means coupled to said bus means for causing the signal levels on said transfer paths to be at a first logic level default state when no transfer is in process; second means for outputting a command cycle signal in response to detecting the transistion of the signal levels on the said transfer paths from said default state to a command subset of transfer path logic levels having at least one of said transfer paths switching from said first logic level of said default state to a second logic level, and means coupled to said memory means, said bus means, and to said second means, for causing said memory means to perform said one of said set of memory cycles in response to said command cycle signal and said common group signal.
Claim 13
Dependent Claim
206 words
A data processing system comprising: bus means for providing transfer paths: processor means coupled to the bus means for selectively transmitting or receiving address, data and command group signals via the bus means, only one of said signals being transferred on the bus means at any given time; memory means coupled to said bus means for selectively storing and outputting data in one of a set of memory cycles responsive to said command signals; first means coupled to said bus means for causing the signal levels on said transfer paths to be at a first logic level default state when no transfer is in process; second means for outputting a command cycle signal in response to detecting the transistion of the signal levels on the said transfer paths from said default state to a command subset of transfer path logic levels having at least one of said transfer paths switching from said first logic level of said default state to a second logic level, and means coupled to said memory means, said bus means, and to said second means, for causing said memory means to perform said one of said set of memory cycles in response to said command cycle signal and said common group signal.
References Cited (Backward Citations)
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