Self-timed programmable logic array with pre-charge circuit

Claim 1

A programmable logic array comprising an input decoder section and an output encoder section connected by a plurality of minterm conductors, said input decoder selecting minterm conductors in response to the encoding of a plurality of input signals, and the output encoder section transmitting a plurality of output signals each on a respective output bit line and having an encoding determined by the selected minterm conductor, A. said input decoder section including a plurality of decoder stages each connected to a node to which one of said minterm conductors is connected, at least some of said decoder stages including at least one control transistor connected to said respective node for controlling the selection of said minterm conductors under control of an input signal, B. said output encoder section including a plurality of stages each connected to a node to which one of said output conductors is connected, at least some of said stages including at least one control transistor connected to said respective node for controlling the transmission of an output signal on said output conductor in response to the selection of said minterm conductor, said programmable logic array further including precharge means for precharging the respective nodes, each of said control transistors being connected between said respective nodes and a switch means and having a control terminal controlled in response to said respective input signal or the selection of said respective ninterm conductors, said switch means being responsive to enabling signals for selectively enabling said control transistors.