Bipolar transistor with polysilicon stringer base contact

Claim 2

A base and emitter structure for a bipolar transistor comprising: an island (30) of monocrystalline silicon of a first conductivity type electrically isolated from adjacent monocrystalline silicon; an emitter region (39) of said first conductivity type within said island; a base region (30) of a second conductivity type within said island and forming a PN junction (43) with said emitter region; an emitter contact (38/40) comprising a strip of polycrystalline silicon (38) of said first conductivity type in electrical contact with said emitter region, the area of said emitter contact lying over said island being smaller than the area the smallest contact window which can be made with the process used to make the base emitter structure defined herein plus the area consumed by the smallest nesting tolerance around all sides of said contact window which can be used in said process, said emitter contact having a top and sides; a layer (42) of insulating material over said emitter contact and self aligned with the sides thereof; insulating spacers (44) formed on at least said side surfaces of said emitter contact over said island; a conductive stringer (46) formed over said island and alongside at least one of said spacers and electrically isolated from said strip by said spacers but in electrical contact with said base region wherein said stringer has an area over said island which is not large enough to encompass a contact window or post via plus the area consumed by the nesting tolerance used in the process used to make the transistor.

Claim 3

The structure of claim 1 wherein said spacers have a width along an axis parallel to said surface of said island which is smaller than the smallest line width, D, which is routinely resolvable by the lithography process used to manufacture the transistor.

Claim 4

The structure of claim 1 wherein said stringers have a width along an axis parallel to said surface of said island which is smaller than the smallest line width, D, which is routinely resolvable by the lithography process used to manufacture the transistor.

Claim 5

The structure of claim 2 wherein said stringers have a width along an axis parallel to said surface of said island which is smaller than the smallest line width, D, which is routinely resolvable by the lithography process used to manufacture the transistor.

Claim 6

The structure of claim 1 wherein said stringers are metal disilicide.

Claim 7

The structure of claim 4 wherein said stringers are refractory metal disilicide.

Claim 8

The structure of claim 6 wherein said spacers are comprised of a layer of thermal oxide adjacent said emitter contact with a layer of CVD oxide overlying said thermal oxide.

Claim 9

The structure of claim 7 wherein said emitter contact includes a layer of metal disilicide in electrical contact with at least part of the top surface of said polycrystalline strip.

Claim 10

The structure of claim 8 wherein said metal disilicide completely covers the top surface of said emitter contact strip and is aligned with the edges defined by said side surfaces thereof and both said disilicide and said emitter contact polysilicon are doped with both N type impurities and P type impurities with the diffusion rate of one type of impurity being greater than the diffusion rate of the other type impurity and wherein said insulating layer is silicon dioxide and overlies the metal disilicide covering the top of said emitter contact strip and is self aligned with the edges thereof.

Claim 11

The structure of claim 1 wherein said emitter region forms a junction with said base region which is approximately equal in area with the area of the emitter contact strip over said island.

Claim 12

The structure of claim 1 wherein the base region forms a base-collector junction (30/36) with said monocrystalline silicon which has approximately the same area as the combined area over the island of said emitter contact plus the areas of the spacers and said stringer or stringers plus any area consumed by lateral diffusion of the impurities from said stringer during the heat drive-in step in the fabrication process.

Claim 13

The structure of claim 1 wherein the base region forms a base-collector junction with said monocrystalline silicon which has approximately the same area as the combined areas over the island of said emitter contact plus the areas of the spacers and said stringer or stringers plus any area consumed by lateral diffusion of the impurities from said stringer during the heat drive-in step in the fabrication process and wherein said emitter region forms a junction with said base region which is approximately equal in area with the area of the emitter contact strip over said island.

Claim 14

The stucture of claim 1 wherein said emitter contact strip extends to a position outside the perimeter of said island and assumes the shape of a contact pad (33) having dimensions sufficient to encompass a contact window (68).

Claim 15

The structure of claim 12 wherein said emitter contact strip extends to a position outside the perimeter of said island and assumes the shape of a contact pad having dimensions sufficient to encompass a contact window.

Claim 16

The structure of claim 1 wherein said stringers extends to a position outside the perimeter of said island and assume the shape of a contact pad having dimensions sufficient to encompass a contact window.

Claim 17

The structure of claim 14 wherein said stringers extends to a position outside the perimeter of said island and assume the shape of a contact pad having dimensions sufficient to encompass a contact window.

Claim 18

A transistor having an isolated island of monocrystalline silicon and an active region formed therein having an active area of two square microns or less.

Claim 19

A transistor having an isolated island of monocrystalline silicon and an active region formed therein having an active area of two square microns or less.

Claim 20

A transistor having an isolated island of monocrystalline silicon and an active region formed therein having an active area of 8 square microns or less.

Claim 21

A transistor having an isolated island of monocrystalline silicon and an active region formed therein having an active area of 8 square microns or less.

Claim 22

A base and emitter structure for an integrated bipolar transistor comprising: a base region of conductive silicon; an emitter region of conductive silicon inside said base region; a conductor in electrical contact with said emitter region; insulating spacers formed on predetermined sides of said conductor; conductive stringers in electrical contact with said base region formed on predetermined sides of said insulating spacers and insulated from said conductor by said spacers, said stringers having a width approximately equal to the depth of the layer of conductive material from which said stringers were formed by anisotropic etching; and means external to said island for making electrical contact with said stringers and with said strip of polysilicon.

Claim 23

A base and emitter structure for an integrated bipolar transistor comprising: a base region of conductive silicon; an emitter region of conductive silicon inside said base region; a conductor in electrical contact with said emitter region; insulating spacers formed on predetermined sides of said conductor; conductive stringers in electrical contact with said base region formed on predetermined sides of said insulating spacers and insulated from said conductor by said spacers, said stringers having a width approximately equal to the depth of the layer of conductive material from which said stringers were formed by anisotropic etching; and means external to said island for making electrical contact with said stringers and with said strip of polysilicon.

Claim 24

A process for making a base and emitter contact structure for a transistor comprising the steps of: forming an isolated island of monocrystalline silicon; forming a layer of polysilicon covered by a first layer of metal disilicide; doping the first metal disilicide layer with both P type and N type impurities where the impurities are selected such that the lower concentration impurity has a faster diffusion rate in terms of distance travelled per unit time for given diffusion conditions; forming a layer of insulating material over said metal disilicide; etching said combined three layers into the shape of an emitter contact stripe which crosses said island and which has an emitter contact pad located external to said island; forming a second layer of insulating material over the etched structure; anisotropically etching the second insulating layer until all the insulating material in planes parallel to the surface of said island is removed; forming a layer of metal disilicide over the structure; doping said second metal disilicide layer with impurities of the conductivity type which will exist in the base region of the final transistor; masking a portion of said second metal disilicide layer which is to be the base contact pad at a location outside said island; anisotropically etching away all portions of said second metal disilicide layer which lie in planes parallel to the surface of said island except that portion under said mask; and baking the resultant structure in an oven long enough and at a temperature sufficient to allow the impurities in said first metal disilicide layer to diffuse into said polysilicon and said monocrystalline silicon sufficiently to form an emitter region of the desired depth and a base region of the desired width which is in electrical contact with said stringers of said second metal disilicide layer.

Claim 25

A process for making a base and emitter contact structure for a transistor comprising the steps of: forming an isolated island of monocrystalline silicon; forming a layer of polysilicon covered by a first layer of metal disilicide; doping the first metal disilicide layer with both P type and N type impurities where the impurities are selected such that the lower concentration impurity has a faster diffusion rate in terms of distance travelled per unit time for given diffusion conditions; forming a layer of insulating material over said metal disilicide; etching said combined three layers into the shape of an emitter contact stripe which crosses said island and which has an emitter contact pad located external to said island; forming a second layer of insulating material over the etched structure; anisotropically etching the second insulating layer until all the insulating material in planes parallel to the surface of said island is removed; forming a layer of metal disilicide over the structure; doping said second metal disilicide layer with impurities of the conductivity type which will exist in the base region of the final transistor; masking a portion of said second metal disilicide layer which is to be the base contact pad at a location outside said island; anisotropically etching away all portions of said second metal disilicide layer which lie in planes parallel to the surface of said island except that portion under said mask; and baking the resultant structure in an oven long enough and at a temperature sufficient to allow the impurities in said first metal disilicide layer to diffuse into said polysilicon and said monocrystalline silicon sufficiently to form an emitter region of the desired depth and a base region of the desired width which is in electrical contact with said stringers of said second metal disilicide layer.

Claim 26

The process of claim 20 wherein the step of doping the first metal disilicide layer includes doping said layer with impurities of two conductivity types where the impurity of the conductivity type that matches the conductivity of the base region to be formed later has a lower concentration thatn the concentration of the other impurity type.

Claim 27

The process of claim 21 where the two impurities are boron and arsenic.

Claim 28

The process of claim 21 wherein said doping step is by ion implantation.

Claim 29

The process of claim 20 wherein the step of forming said second insulating layer comprises the steps of thermally growing a layer of silicon dioxide followed by chemical vapor deposition of another layer of silicon dioxide.

Claim 30

The process of claim 24 wherein the chemical vapor deposition step continues until approximately 2000 to 5000 Å of oxide exist over the structure.

Claim 31

The process of claim 20 wherein the step of forming the second layer of metal disilicide is carried out such the second layer of metal disilicide forms over all parts of the structure and approximately 2000 to 5000 Å have been formed.

Claim 32

The process of claim 20 wherein the step of etching the combined three layers of polysilicon, metal disilicide and oxide comprises etching isotropically with a controlled lateral etch rate to form an etched image of the emitter contact stripe which is smaller in width than the etch mask image.

Claim 33

The process of claim 20 further comprising the step of selectively removing the stringer of metal disilicide from said second layer of metal disilicide from around said emitter contact pad.