EP0251023A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A circuit for biasing a magnetoresistive sensor and amplifying signals produced thereby
Assignee: International Business Machines Corp
•
Filing: 1987-06-16
•
Granted: —
•
Expires: 2007-06-16
Abstract
Abstract The resistance (Rh) of a magnetoresistive sensor is disposed between the bases of a differential pair of transistors (T1a and T1b) comprising the input stage of an amplifier. Constant bias voltage for the sensor is provided (by J1 and RE) independently of the resistance of the sensor. DC feedback (from g₀) to the input stage balances current flow in both paths of the differential input stage to correct for DC offset arising in the output from the input stage emitter resistor (RE). The amplified signal represents ΔR h /R h , where ΔR h is the change in steady-state resistance, R h , of the sensor.
Inventors
- 👤 Stephen Alan Jove
- 👤 Klaas Berend Klaassen
- 👤 Calvin Shizuo Nomura
- 👤 Jacobus Cornelis Leonardus Van Peppen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 14:06
CPC Classifications
G; G01; G01R; G01R33/00; G01R33/02; G01R33/06; G01R33/09; G11; G11B; G11B5/00; G11B5/02; G11B2005/0002; G11B2005/0005; G11B2005/001; G11B2005/0013; G11B2005/0016
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
109 words
A circuit for simultaneously biasing and amplifying signals produced by a magnetoresistive sensor, said circuit comprising: a magnetoresistive sensor (Rh) having a steady-state resistance value; a bias means (J1, RE) to provide a bias voltage having a constant time average value across said sensor; an input stage, having at least two transistors (T1a, T1b) coupled in differential pair configuration and having the magnetoresistive sensor (Rh) coupled between the bases of said pair of transistors, for amplifying voltage deviations from said constant time average value of the voltage across the magnetoresistive sensor; and an output stage (G, g₀), coupled to the input stage, for amplifying and transmitting signals received therefrom.
Claim 2
Dependent Claim
109 words
A circuit for simultaneously biasing and amplifying signals produced by a magnetoresistive sensor, said circuit comprising: a magnetoresistive sensor (Rh) having a steady-state resistance value; a bias means (J1, RE) to provide a bias voltage having a constant time average value across said sensor; an input stage, having at least two transistors (T1a, T1b) coupled in differential pair configuration and having the magnetoresistive sensor (Rh) coupled between the bases of said pair of transistors, for amplifying voltage deviations from said constant time average value of the voltage across the magnetoresistive sensor; and an output stage (G, g₀), coupled to the input stage, for amplifying and transmitting signals received therefrom.
Claim 3
Dependent Claim
64 words
A circuit as claimed in claim 1, wherein: the input stage further includes an emitter resistor coupled between the emitters of said differential pair, the emitter of one of said differential pair being coupled to a first constant current source; and said bias voltage is referenced to a voltage produced by a current from said first constant current source flowing through said emitter resistor.
Claim 4
Dependent Claim
23 words
A circuit as claimed in claim 2, wherein the current flowing in each of the emitters of said differential pair is substantially equal.
Claim 5
Dependent Claim
32 words
A circuit as claimed in any preceding claim, further including feedforward means, coupled to the input and output stages, for controlling the DC offset voltage at the output of the output stage.
Claim 6
Dependent Claim
20 words
A circuit as claimed in any preceding claim, wherein the output stage comprises two resistors having substantially equal resistance value.
Claim 7
Dependent Claim
23 words
A circuit as claimed in any preceding claim, wherein the current flowing in each transistor of the first differential pair is substantially equal.
Claim 8
Dependent Claim
28 words
A circuit as claimed in any preceding claim including feedback means coupled from the output stage to the input stage, for correcting variations in said bias voltage levels.
Claim 9
Dependent Claim
43 words
A circuit as in claimed in claim 7, wherein the collectors and bases of the said first differential pair of transistors are coupled to the feedback means, and the emitters of said first differential pair are coupled to the first constant current source.
Claim 10
Dependent Claim
94 words
A circuit as claimed in claim 7 or claim 8, wherein the feedback means includes: at least two transistors coupled in a second differential pair configuration for correcting the voltage at the bases of the first differential pair; and first and second follower transistors, coupled to the first differential pair, for coupling the variations in the voltage levels produced in the input stage to the second differential pair; said second differential pair being coupled to a second constant current source, and said follower transistors being coupled to third and fourth constant current sources, respectively.
Claim 11
Dependent Claim
27 words
A circuit as claimed in any of claims 7 to 9, wherein the feedback means includes frequency setting means for setting the frequency response of the circuit.
Claim 12
Dependent Claim
15 words
A circuit as claimed in claim 10, wherein the frequency setting means is a capacitor.
Claim 13
Dependent Claim
37 words
A circuit as claimed in any preceding claim, further including: a plurality of input stages; and selection means for activating one of the plurality of input stages and deactivating all of the remaining plurality of input stages.
Claim 14
Dependent Claim
48 words
A circuit as claimed in claim 12, further including settling means for reducing the time required for said circuit to settle into steady-state operation after one of said plurality of input stages is deactivated and another of said input stages is activated or after activating any input stage.
Claim 15
Dependent Claim
36 words
A circuit as claimed in claim 13, wherein the settling means comprise control means for temporarily increasing the available output drive current of said feedback means during activation of any of said plurality of input stages.
Claim 16
Dependent Claim
51 words
A circuit as in claim 13, wherein the settling means comprises first and second comparator means coupled to the output of said input stage for controlling the DC offset voltage thereat in response to a change in such DC offset voltage during deactivation of one and activation of another input stage.
Claim 17
Dependent Claim
24 words
A circuit as claimed in any of claims 13 to 15, wherein said selection means is effective for deactivating all of said input stages.
Claim 18
Dependent Claim
121 words
A circuit for simultaneously biasing a magnetoresistive sensor having a steady-state resistance value and amplifying signals produced by the sensor when it is exposed to a changing magnetic field, the circuit comprising: first means responsive to the voltage across the sensor to produce signals representing the change in sensor resistance arising from changes in the magnetic field to which the sensor is exposed; second means coupled to the first means for amplifying the signals produced thereby, and having an output for transmitting said amplified signals therefrom; third means coupled to the first and second means for setting the frequency response of the circuit; and fourth means coupled to the second means for substantially eliminating DC offset voltage at the output thereof.
Claim 19
Dependent Claim
121 words
A circuit for simultaneously biasing a magnetoresistive sensor having a steady-state resistance value and amplifying signals produced by the sensor when it is exposed to a changing magnetic field, the circuit comprising: first means responsive to the voltage across the sensor to produce signals representing the change in sensor resistance arising from changes in the magnetic field to which the sensor is exposed; second means coupled to the first means for amplifying the signals produced thereby, and having an output for transmitting said amplified signals therefrom; third means coupled to the first and second means for setting the frequency response of the circuit; and fourth means coupled to the second means for substantially eliminating DC offset voltage at the output thereof.
Claim 20
Dependent Claim
30 words
A circuit as claimed in claim 17, wherein error signals produced by the third means are subtracted from the signals produced by the first means to provide preselectable frequency response.
Claim 21
Dependent Claim
17 words
A circuit as claimed in claim 17 or claim 18, wherein the third means includes a capacitor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.