EP0250171A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Compound semiconductor devices
Assignee: Massachusetts Institute of Technology
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Filing: 1987-06-12
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Granted: —
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Expires: 2007-06-12
Abstract
Abstract Monolithic integration of Si MOSFETs (10) and gallium arsenide MESFETs (100) on a silicon substrate (12) is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers (14 to 17) of SiO₂ and Si₃N₄ to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs (100) are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si₃N₄/SiO₂ layers and final metallization is performed to complete the MOSFET fabrication. In an alternative embodiment, Si MOSFETs and aluminum gallium arsenide double heterostructure LEDs are formed in a similar manner.
Inventors
- 👤 Hong Kyun Choi
- 👤 Bor-Yeu Tsaur
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 00:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/08; H10D84/0123; H10D84/0126; H10D84/0158; H10D86/00; H10D86/01; H10D86/03; H10D87/00; H10H; H10H29/00; H10H29/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/072; Y10S148/097; Y10S148/149; Y10S438/00; Y10S438/973
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
130 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate; (b) forming a protective layer over the Si devices and the remainder of said substrate; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) forming ohmic contacts on said devices.
Claim 2
Independent Claim
130 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate; (b) forming a protective layer over the Si devices and the remainder of said substrate; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) forming ohmic contacts on said devices.
Claim 3
Dependent Claim
27 words
A method as claimed in claim 1, characterised by forming interconnects for the Si devices and compound semiconductor devices and between the Si and compound semiconductor devices.
Claim 4
Dependent Claim
26 words
A method as claimed in claim 1, characterised in that the substrate comprises a single crystal: silicon, or a silicon on sapphire, or a silicon-on-insulator substrate.
Claim 5
Dependent Claim
18 words
A method as claimed in claim 1, characterised in that the protective layer comprises a layer of SiO₂.
Claim 6
Dependent Claim
19 words
A method as claimed in claim 1, characterised in that the protective layer comprises layers of SiO₂ and Si₃N₄.
Claim 7
Dependent Claim
19 words
A method as claimed in claim 1, characterised in that the compound semiconductor is GaAs or an alloy thereof.
Claim 8
Dependent Claim
19 words
A method as claimed in claim 6, characterised in that the gallium arsenide semiconductor device is an optoelectronic device.
Claim 9
Dependent Claim
19 words
A method as claimed in claim 1, characterised in that the Si devices are part of an Si circuit.
Claim 10
Dependent Claim
27 words
A method as claimed in claim 1, characterised in that the compound semiconductor devices are transistors from the class comprising MESFETs, bipolar transistors, or modulation doped FETs.
Claim 11
Dependent Claim
26 words
A method as claimed in claim 1, characterised in that the compound semiconductor devices are optoelectronic devices from the class comprising LED, lasers and light detectors.
Claim 12
Dependent Claim
25 words
A method as claimed in claim 1, characterised in that the compound semiconductor devices are part of a circuit consisting of transistors and optoelectronic devices.
Claim 13
Dependent Claim
42 words
A method as claimed in claim 1, characterised in that prior to step (b) heavily doped n+ islands are formed adjacent and in contact with doped regions of said Si devices to form low resistance interconnection paths to said compound semiconductor device.
Claim 14
Dependent Claim
34 words
A method as claimed in claim 1, characterised in that the silicon devices are formed on selected areas of a silicon single crystal wafer which is oriented at an angle offf the crystallographic plane.
Claim 15
Dependent Claim
23 words
A method as claimed in claim 13, characterised in that the orientation is 3° off the 100 crystallographic plane toward the 111 plane.
Claim 16
Dependent Claim
47 words
A method as claimed in claim 1, characterised in that the ohmic contacts for said Si devices and compound semiconductor devices is formed after the compound semiconductor device is formed and the ohmic contacts for the Si devices is formed through openings made in said protective layer.
Claim 17
Independent Claim
117 words
A method of fabricating semiconductor devices of gallium arsenide and semiconductor devices of silicon on a common Si, SOS, or SOI substrate surface comprising the steps of: (a) forming silicon devices on selected regions of said surface; (b) forming a protective layer over said devices and substrate; (c) forming openings laterally displaced from said devices through said protective layer to expose additional regions of the surface of said substrate; (d) forming a gallium arsenide layer over the protective layer and the exposed surface regions; (e) removing the gallium arsenide layer except at the exposed surface regions; (f) forming a gallium arsenide semiconductor device on the remaining gallium arsenide layer; and (g) forming ohmic contacts on said devices.
Claim 18
Independent Claim
117 words
A method of fabricating semiconductor devices of gallium arsenide and semiconductor devices of silicon on a common Si, SOS, or SOI substrate surface comprising the steps of: (a) forming silicon devices on selected regions of said surface; (b) forming a protective layer over said devices and substrate; (c) forming openings laterally displaced from said devices through said protective layer to expose additional regions of the surface of said substrate; (d) forming a gallium arsenide layer over the protective layer and the exposed surface regions; (e) removing the gallium arsenide layer except at the exposed surface regions; (f) forming a gallium arsenide semiconductor device on the remaining gallium arsenide layer; and (g) forming ohmic contacts on said devices.
Claim 19
Dependent Claim
32 words
A method as claimed in claim 16, characterised in that low resistance interconnection between the Si devices and the gallium arsenide devices is made during the formation of the gallium arsenide layer.
Claim 20
Dependent Claim
33 words
A method as claimed in claim 17, characterised in that the interconnection comprises a heavily doped Si region in contact with a portion of said Si devices and underlying the gallium arsenide device.
Claim 21
Dependent Claim
18 words
A method as claimed in claim 16, characterised in that the protective layer comprises a layer of SiO₂.
Claim 22
Dependent Claim
19 words
A method as claimed in claim 16, characterised in that the protective layer comprises layers of SiO₂ and Si₃N₄.
Claim 23
Dependent Claim
27 words
A method as claimed in claim 16, characterised in that the ohmic contacts for said silicon devices is made after said gallium arsenide semiconductor device is formed.
Claim 24
Dependent Claim
26 words
A method as claimed in claim 16, characterised in that the ohmic contacts for said silicon devices is made through openings formed in said protective layer.
Claim 25
Dependent Claim
29 words
A semiconductor circuit comprising gallium arsenide devices and silicon devices formed on a common silicon substrate upon which are formed silicon devices and laterally displaced therefrom gallium arsenide devices.
Claim 26
Dependent Claim
29 words
A semiconductor circuit comprising gallium arsenide devices and silicon devices formed on a common silicon substrate upon which are formed silicon devices and laterally displaced therefrom gallium arsenide devices.
Claim 27
Dependent Claim
42 words
A circuit as claimed in claim 23, characterised in that the silicon devices are protected by a layer of silicon dioxide/silicon nitride through which metallization is provided for ohmic contacts to silicon-doped regions in the silicon device contained in the silicon substrate.
Claim 28
Dependent Claim
58 words
A monolithic integrated circuit of gallium arsenide and silicon formed on a common silicon substrate upon which is formed silicon devices and laterally displaced therefrom gallium arsenide devices and wherein the silicon devices are protected by a layer through which metallization is provided for ohmic contacts to silicon-doped regions in the silicon device contained in the silicon substrate.
Claim 29
Dependent Claim
58 words
A monolithic integrated circuit of gallium arsenide and silicon formed on a common silicon substrate upon which is formed silicon devices and laterally displaced therefrom gallium arsenide devices and wherein the silicon devices are protected by a layer through which metallization is provided for ohmic contacts to silicon-doped regions in the silicon device contained in the silicon substrate.
Claim 30
Dependent Claim
31 words
A circuit as claimed in claim 25, characterised in that the silicon devices and gallium arsenide devices are interconnected by a low resistance path of heavily doped silicon between device elements.
Claim 31
Dependent Claim
61 words
A circuit as claimed in claim 25, characterised in that the silicon device is a MOSFET having gate, drain and source regions and the gallium arsenide device is an LED having an anode and cathode and the drain region of the MOSFET is connected to the cathode of the LED by a heavily doped region of Si formed below the LED.
Claim 32
Independent Claim
217 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate with low resistance interconnections between the compound semiconductor devices and the silicon devices formed in the substrate comprising the steps of: (a) forming Si devices having junctions formed of opposite conductivity regions and wherein one of said regions extends laterally along the planar surface of the substrate on selected areas of a planar surface of said substrate; (b) forming a protective layer over the Si devices and the remainder of said substrate surface; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate, a portion of the perimeter of said openings being coextensive with said extended region; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices having junctions formed of opposite conductivity regions on the remaining single crystalline compound semiconductor with one of said regions contacting said extended region of said Si devices to form said low resistance interconnection in said substrate; and (g) forming ohmic contacts on said devices.
Claim 33
Independent Claim
217 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate with low resistance interconnections between the compound semiconductor devices and the silicon devices formed in the substrate comprising the steps of: (a) forming Si devices having junctions formed of opposite conductivity regions and wherein one of said regions extends laterally along the planar surface of the substrate on selected areas of a planar surface of said substrate; (b) forming a protective layer over the Si devices and the remainder of said substrate surface; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate, a portion of the perimeter of said openings being coextensive with said extended region; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices having junctions formed of opposite conductivity regions on the remaining single crystalline compound semiconductor with one of said regions contacting said extended region of said Si devices to form said low resistance interconnection in said substrate; and (g) forming ohmic contacts on said devices.
References Cited (Backward Citations)
DE3404875A1
Cited
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