EP0250160A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Combined circuit switch and packet switching system
Assignee: AT&T Inc
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Filing: 1987-06-11
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Granted: —
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Expires: 2007-06-11
Abstract
Abstract Apparatus (FIG. 3) for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus (320). A memory (l04C) having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not presently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by the receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.
Inventors
- 👤 James Joseph Ferenc
- 👤 Robert William Gebhardt
- 👤 Gary Joe Grimes
- 👤 Edward Bernard Morgan, Jr.
- 👤 Gabe Alfred Sellers, Iii.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 14:47
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/16; H04J3/1682
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
166 words
Apparatus for transmitting circuit switch and packet information over a time multiplexed bus (l09), said apparatus comprising: a circuit switching network (l02) for generating a time multiplexed signal comprising cyclically reoccurring frames of information with each of said frames comprising a plurality of time slots and with said circuit switch information being contained in only certain ones of said time slots with the remainder of said time slots being idle, a packet switching network (l03), multiplexor (l05), CHARACTERIZED IN THAT a controller (l04) for controlling said multiplexor to transmit said circuit switch and packet information over said bus by inserting presently extant packet information into said presently idle time slots so that all of said idle time slots are used to transmit any extant packet information, and inserter circuit (ll0, lll) intermediate between said multiplexor and said circuit and packet switching networks for inserting identity information into each time slot representing the type of information represented by the information in the remainder of said time slot.
Claim 2
Dependent Claim
166 words
Apparatus for transmitting circuit switch and packet information over a time multiplexed bus (l09), said apparatus comprising: a circuit switching network (l02) for generating a time multiplexed signal comprising cyclically reoccurring frames of information with each of said frames comprising a plurality of time slots and with said circuit switch information being contained in only certain ones of said time slots with the remainder of said time slots being idle, a packet switching network (l03), multiplexor (l05), CHARACTERIZED IN THAT a controller (l04) for controlling said multiplexor to transmit said circuit switch and packet information over said bus by inserting presently extant packet information into said presently idle time slots so that all of said idle time slots are used to transmit any extant packet information, and inserter circuit (ll0, lll) intermediate between said multiplexor and said circuit and packet switching networks for inserting identity information into each time slot representing the type of information represented by the information in the remainder of said time slot.
Claim 3
Independent Claim
73 words
The apparatus of claim l wherein said multiplexor has a first input for receiving said time slot multiplexed signal from said circuit switching network and a second input for receiving said packet information, and an output on said multiplexor connected to said bus, said multiplexor being effective controllably to connect said output to said first and second inputs, respectively, during occurrences of time slots serving said circuit switch and said packet information, respectively.
Claim 4
Dependent Claim
37 words
The apparatus of claim 2 (FIG. 3) further comprises a serial link formatter (306) for forming n of said time slots containing said inserted identity information into subframes having 2 n1 bits where nl is an integer.
Claim 5
Independent Claim
159 words
The apparatus of claim l in combination with receiving apparatus (FIG. 4) for receiving said information transmitted over said bus, said receiving apparatus comprising: a circuit switch interface (l25) and a packet switch interface (l26), a time slot formatter (402) for applying bits of each transmitted time slot to each of said interfaces, a register (403) in said packet switch interface for determining from said inserted identity information whether the other bits of each time slot comprise circuit switch or packet switch information, a receiving packet switching network and a receiving circuit switching network, a recognizer and controller circuit (404, 405) for extending the bits of a received time slot to said receiving packet switch only if said inserted information indicates that the other bits of said time slot comprise packet information, and a gate circuit (407) in said circuit switch interface for extending to said circuit switch the bits of each received time slot representing circuit switch information.
Claim 6
Independent Claim
144 words
A method of operating apparatus for transmitting circuit switch and packet information over a time multiplexed bus (l09), said method comprising the steps of: l) generating a time multiplexed signal comprising cyclically reoccurring frames of information with each of said frames comprising a plurality of time slots and with said circuit switch information being contained in only certain ones of said time slots with the remainder of said time slots being idle, CHARACTERIZED IN THAT 2) controlling a multiplexor (l05) to transmit said circuit switch and packet information over said bus by inserting presently extant packet information into said presently idle time slots so that all of said idle time slots are used to transmit any extant packet information, and 3) inserting identity information into each time slot representing the type of information represented by the information in the remainder of said time slot.
Claim 7
Independent Claim
144 words
A method of operating apparatus for transmitting circuit switch and packet information over a time multiplexed bus (l09), said method comprising the steps of: l) generating a time multiplexed signal comprising cyclically reoccurring frames of information with each of said frames comprising a plurality of time slots and with said circuit switch information being contained in only certain ones of said time slots with the remainder of said time slots being idle, CHARACTERIZED IN THAT 2) controlling a multiplexor (l05) to transmit said circuit switch and packet information over said bus by inserting presently extant packet information into said presently idle time slots so that all of said idle time slots are used to transmit any extant packet information, and 3) inserting identity information into each time slot representing the type of information represented by the information in the remainder of said time slot.
Claim 8
Dependent Claim
46 words
The method of claim 5 wherein said step of transmitting said circuit switch and said packet information over said bus comprises the step of: forming n of said time slots containing said inserted identity information into subframes having 2 n1 bits where nl is an integer.
Claim 9
Dependent Claim
133 words
The method of claim 6 in combination with a method of operating receiving apparatus for receiving said information transmitted over said bus, said last named method comprising the steps of: l) applying bits of each transmitted time slot to a circuit switch interface (l25) and to a packet switch interface (l26), 2) operating said packet switch interface for determining from said inserted identity information of each time slot whether the other bits of said time slot comprise circuit switch or packet switch information, 3) extending the bits of a received time slot to a receiving packet switch only if said inserted information indicates that the other bits of said time slot comprise packet information, and 4) extending to a receiving circuit switch the bits of each received time slot representing circuit switch information.
Claim 10
Dependent Claim
161 words
The method of claim 7 in combination with a method of operating said circuit switch interface said method comprising the steps of: l) writing an indication in each location of a receiving memory (408) having a location individual to each received time slot with said indication specifying whether the time slot individual to each said location is presently assigned to serve said circuit switch information or said packet information, 2) reading out the contents of said receiving memory location individual to each said received time slot during each occurrence of each received time slot, 3) applying said read out contents of said receiving memory to a comparator (407) during each occurrence of each of said received time slot, and 4) applying said inserted identity information of each time slot to said comparator, said comparator being responsive to the receipt of said identity information and from said memory to indicate a correspondence or non-correspondence between said received information and said readout contents.
Claim 11
Dependent Claim
98 words
The method of claim 9 in combination with the steps of: l) inserting message information into successive occurrences of one of said transmitted time slots with said message information specifying which of said time slots are serving said circuit switch information and which of said time slots are serving said packet information, 2) operating said receiving apparatus to receive said message information, and 3) writing information into said receiving memory responsive to the receipt of said message information specifying the type of information that is being served by each of said time slots received by said receiving apparatus.
References Cited (Backward Citations)
No citation records indexed.
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