Vertical driving pulse generating circuit

Claim 2

A vertical driving pulse generating circuit for determining whether or not a period of a vertical synchronizing signal included in a video signal to be displayed coincides with a predetermined normal vertical scanning period and generating a vertical driving pulse having the same period as that of said vertical synchronizing signal when they do not coincide with each other and a vertical driving pulse having the same period as that of the normal vertical scanning period when they coincide with each other, comprising: vertical synchronizing signal separating means (9) for separating a vertical synchronizing signal included in said video signal, clock signal inputting terminal (12) for inputting a clock signal having a frequency of N (N is a positive integer) times a predetermined normal horizontal scanning frequency, signal generating means (11) responsive to said clock signal for generating a timing signal having the same period as said normal vertical scanning period and said vertical driving pulse, input selecting means (13) receiving the vertical synchronizing signal separated by said vertical synchronizing signal separating means and said timing signal for selecting and outputting one of them, reset pulse generating means (14) responsive to an output of said input selecting means for generating a reset pulse for resetting said signal generating means, and phase comparing means (19) for comparing phases of said timing signal and said reset pulse and controlling selection by said input selecting means depending on whether or not the phases coincide with each other, said signal generating means being reset with the same period as the vertical- synchronizing signal and generating a vertical driving pulse having the same period as that of the vertical synchronizing signal when said input selecting means selects said vertical synchronizing signal, and being reset with a constant period defined by the timing signal and generating a vertical driving pulse having the constant period when said input selecting means selects said timing signal.

Claim 3

A vertical driving pulse generating circuit for determining whether or not a period of a vertical synchronizing signal included in a video signal to be displayed coincides with a predetermined normal vertical scanning period and generating a vertical driving pulse having the same period as that of said vertical synchronizing signal when they do not coincide with each other and a vertical driving pulse having the same period as that of the normal vertical scanning period when they coincide with each other, comprising: vertical synchronizing signal separating means (9) for separating a vertical synchronizing signal included in said video signal, clock signal inputting terminal (12) for inputting a clock signal having a frequency N (N is a positive integer) times a predetermined normal horizontal scanning frequency to a television signal, signal generating means (11) responsive to said clock signal for generating a plurality of timing signals which are in synchronization with the clock signal and said vertical driving pulse, input selecting means (13) receiving the vertical synchronizing signal separated by said vertical synchronizing signal separating means (9) and a first timing signal having the same period as said normal vertical scanning period out of said plurality of timing signals for selecting and outputting one of them, reset pulse generating means (14) responsive to an output of said input selecting means for generating a reset pulse for resetting said signal generating means, signal selecting means (18) for selecting and outputting said reset pulse and said first timing signal or said vertical synchronizing signal and a second timing signal out of said plurality of timing signals, and phase comparing means (19) for comparing phases of two signals selectively outputted from said signal selecting. means and controlling selection by said input selecting means and said signal selecting means depending on whether or not the phases coincide with each other, said signal generating means being reset with the same period as that of the vertical synchronizing signal and generating a vertical driving pulse with the same period as that of the vertical synchronizing signal when said input selecting means selects said vertical synchronizing signal, and being reset with a constant period defined by the first timing signal and generating a vertical driving pulse with the constant period when said input selecting means selects said first timing signal.

Claim 4

A vertical driving pulse generating circuit for determining whether or not a period of a vertical synchronizing signal included in a video signal to be displayed coincides with a predetermined normal vertical scanning period and generating a vertical driving pulse having the same period as that of said vertical synchronizing signal when they do not coincide with each other and a vertical driving pulse having the same period as that of the normal vertical scanning period when they coincide with each other, comprising: vertical synchronizing signal separating means (9) for separating a vertical synchronizing signal included in said video signal, clock signal inputting terminal (12) for inputting a clock signal having a frequency N (N is a positive integer) times a predetermined normal horizontal scanning frequency to a television signal, signal generating means (11) responsive to said clock signal for generating a plurality of timing signals which are in synchronization with the clock signal and said vertical driving pulse, input selecting means (13) receiving the vertical synchronizing signal separated by said vertical synchronizing signal separating means (9) and a first timing signal having the same period as said normal vertical scanning period out of said plurality of timing signals for selecting and outputting one of them, reset pulse generating means (14) responsive to an output of said input selecting means for generating a reset pulse for resetting said signal generating means, signal selecting means (18) for selecting and outputting said reset pulse and said first timing signal or said vertical synchronizing signal and a second timing signal out of said plurality of timing signals, and phase comparing means (19) for comparing phases of two signals selectively outputted from said signal selecting. means and controlling selection by said input selecting means and said signal selecting means depending on whether or not the phases coincide with each other, said signal generating means being reset with the same period as that of the vertical synchronizing signal and generating a vertical driving pulse with the same period as that of the vertical synchronizing signal when said input selecting means selects said vertical synchronizing signal, and being reset with a constant period defined by the first timing signal and generating a vertical driving pulse with the constant period when said input selecting means selects said first timing signal.

Claim 5

A vertical driving pulse generating circuit in accordance with claim 2, wherein said signal generating means comprises frequency dividing means (11a-11j) for frequency-dividing said clock pulse, and decoding means (11 k-11 r) for decoding an output of said frequency dividing means.

Claim 6

A vertical driving pulse generating circuit in accordance with claim 2, further comprising: first gate means (16) for passing a vertical synchronizing signal which arrives with the same period as said predetermined normal vertical scanning period out of vertical synchronizing signals separated by said vertical synchronizing signal separating means, and holding means (17) for holding an output of said first gate means during a predetermined period and applying the same to said signal selecting means.

Claim 7

A vertical driving pulse generating circuit in accordance with claim 4, wherein said first gate means is set to have the gate opening period in which a vertical synchronizing signal having a predetermined normal period and a vertical synchronizing signal having a period which slightly deviates from said period can pass through said first gate means.

Claim 8

A vertical driving pulse generating circuit in accordance with claim 5, wherein opening or closing of said first gate means is controlled by a third timing signal out of a plurality of timing signals generated from said signal generating means.

Claim 9

A vertical driving pulse generating circuit in accordance with claim 2, wherein said phase comparing means comprises complementary output generating means (19a) for generating two logical outputs having complementary relation, depending on whether or not phases of two signals outputted from said signal selecting means coincide with each other, second gate means (19b or 19c) responsive to . one output of said complementary output generating means for gating a fourth signal out of said plurality of timing signals, third gate means (19c or 19b) responsive to the other output of said complementary output generating means for gating said fourth timing signal, first counting means (19d or 19e) for counting pulses of said fourth timing signal which passed through said second gate means and completing counting when the count attains a predetermined value, second counting means (19e or 19d) for counting pulses of said fourth timing signal which passed through said third gate means and completing counting when the count attains a predetermined value, and state storing means (19f) for storing a, first state in response to an output signal caused by completion of counting of one of said first and second counting means and storing a second state in response to an output signal caused by the other completion of counting.

Claim 10

A vertical driving pulse generating circuit in accordance with claim 7, wherein said first and second counting means have the different values of completion of counting, one being reset in response to the completion of counting by the other.

Claim 11

A vertical driving pulse generating circuit in accordance with claim 2, wherein said vertical driving pulse is applied to a television receiver, and which further comprises: channel switching signal inputting means (29) for inputting a channel switching signal indicating that a channel switching is made in said television receiver, and means (27, 28) responsive to said channel switching signal for inverting a phase comparing output of said phase comparing means.