EP0249985A2
Expired / Lapsed
EP
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Video memory
Assignee: Sony Corp
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Filing: 1987-06-19
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Granted: —
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Expires: 2007-06-19
Abstract
Abstract A video memory, for use with a video tape recorder, a television receiver of the like to process a picture, is simplified and can achieve the functions of a time base corrector, a noise reduced and a comb filter, so as to considerably improve the quality of a video picture. A frequency converting circuit for use with the video memory includes a comparator (30) for comparing first and second address signals and an address correction circuit (38) connected to receive an output signal from the comparator (30). When a crossing occurs between the first and second address signals, the sequential order in which an address signal is supplied to the memory (12) is switched by the address correcting circuit (38), to thereby derive a continuous output signal from the memory (12).
Inventors
- 👤 Norio Ebihara
- 👤 Takayuki Sasaki
- 👤 Hiroyuki Kita
- 👤 Yoshihito Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:31
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036; H; H04; H04N; H04N5/00; H04N5/76; H04N5/907; H04N9/00; H04N9/79; H04N9/87; H04N9/877
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
79 words
A video memory apparatus comprising: a) input buffer means (11) supplied with an input video signal; b) memory means (12) connected to receive and store an output of said input buffer means; and c) first and second output buffer means (16,18) connected to said memory means for alternately receiving outputs of said memory means, wherein said input buffer means and at least either said first or second output buffer means are operated in an asynchronous relation to each other.
Claim 2
Dependent Claim
79 words
A video memory apparatus comprising: a) input buffer means (11) supplied with an input video signal; b) memory means (12) connected to receive and store an output of said input buffer means; and c) first and second output buffer means (16,18) connected to said memory means for alternately receiving outputs of said memory means, wherein said input buffer means and at least either said first or second output buffer means are operated in an asynchronous relation to each other.
Claim 3
Dependent Claim
40 words
Apparatus according to Claim 1, including first and second address means (14,14A) for manifesting addresses of said memory means and for causing said memory means to read out data from said addresses to said first and second output buffers, respectively.
Claim 4
Dependent Claim
23 words
Apparatus according to Claim 2, including third address means (13) for manifesting addresses at which data from said input buffer means is stored.
Claim 5
Dependent Claim
28 words
Apparatus according to Claim 1, wherein said first and second output buffers are clocked memory units, each being connected to an independent source of clock pulses (CKR1, CKR2).
Claim 6
Dependent Claim
74 words
Apparatus according to Claim 1, wherein said input buffer means (11) comprises a memory for accepting serial input data and for transferring a plurality of bits of said input data in parallel to said memory means, and said first and second output buffer means (16, 18) each comprises a memory for accepting a plurality of data bits from said memory in parallel, and for providing data in series to first and second outputs, respectively.
Claim 7
Dependent Claim
149 words
A frequency converting circuit having an addressable memory (12) in which an input signal is written at a predetermined address in response to a first address signal and data written in the predetermined address of said memory is read out therefrom in response to a second address signal to provide a frequency-converted output signal, comprising: a) comparing means (30) for comparing said first and second address signals with each other and for producing a coincidence signal; and b) an address correcting circuit (38) connected to receive an output of said comparing means, wherein said coincidence signal is produced to indicate a crossing between said first and second address signals, and switch means (31,32, 34) connected to said address correcting circuitry, whereby the state of the address signals supplied subsequently to said memory is switched by said address correcting circuit to thereby derive a continuous output signal from said memory.
Claim 8
Dependent Claim
149 words
A frequency converting circuit having an addressable memory (12) in which an input signal is written at a predetermined address in response to a first address signal and data written in the predetermined address of said memory is read out therefrom in response to a second address signal to provide a frequency-converted output signal, comprising: a) comparing means (30) for comparing said first and second address signals with each other and for producing a coincidence signal; and b) an address correcting circuit (38) connected to receive an output of said comparing means, wherein said coincidence signal is produced to indicate a crossing between said first and second address signals, and switch means (31,32, 34) connected to said address correcting circuitry, whereby the state of the address signals supplied subsequently to said memory is switched by said address correcting circuit to thereby derive a continuous output signal from said memory.
Claim 9
Dependent Claim
59 words
Apparatus according to Claim 6, wherein said address correcting circuitry includes a pair of flip-flops (31,32) connected to receive said coincidence signal and for manifesting a first output signal when said first address signal overtakes and crosses said second address signal and for manifesting a second output when said second address signal overtakes and crosses said first address signal.
Claim 10
Dependent Claim
54 words
Apparatus according to Claim 6, including a delay unit (36) for selectively delaying delivery of an output of said memory to an output terminal, said switch means being connected to said memory and to said delay unit and to said output terminal for selectively interposing said delay unit in circuit with said output terminal.
Claim 11
Dependent Claim
71 words
Video memory apparatus comprising a frame memory (20), an adder unit (3) having a video signal connected to one input and having its output (10) connected to an input of said frame memory, first and second output terminals (17,19) connected to receive separate outputs of said frame memory, and means for connecting only one of said two outputs through a multiplier unit (5) to an input of said adder unit (3).
Claim 12
Dependent Claim
71 words
Video memory apparatus comprising a frame memory (20), an adder unit (3) having a video signal connected to one input and having its output (10) connected to an input of said frame memory, first and second output terminals (17,19) connected to receive separate outputs of said frame memory, and means for connecting only one of said two outputs through a multiplier unit (5) to an input of said adder unit (3).
Claim 13
Dependent Claim
67 words
Video memory apparatus comprising a frame memory (20) for storing frames of video data, said frame memory having first and second outputs (17,19) for manifesting data stored in said memory corresponding to successive frames, and adder means (3) connected to said first and second outputs for adding data corresponding to said successive frames for producing an output signal corresponding to the luminance component of said video signal.
Claim 14
Dependent Claim
67 words
Video memory apparatus comprising a frame memory (20) for storing frames of video data, said frame memory having first and second outputs (17,19) for manifesting data stored in said memory corresponding to successive frames, and adder means (3) connected to said first and second outputs for adding data corresponding to said successive frames for producing an output signal corresponding to the luminance component of said video signal.
References Cited (Backward Citations)
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