EP0249962A2
Expired / Lapsed
EP
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Digital video signal processor
Assignee: Hitachi Ltd
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Filing: 1987-06-16
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Granted: —
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Expires: 2007-06-16
Abstract
Abstract According to the present invention, the number of elements of a signal processing circuit or the like can be drastically reduced by conducting a'time-multiplex processing. In a transversal filter having a coefficient of symmetry of 16 taps, for example, the prior art requires about 58 000 transistors. In case four signal processing cores (i.e., SPC) having a function of four taps are used, the number of transistors required can be reduced to about 34 000 by a duplexing process. In case two SPCs having a function of eight taps are used, the number can be reduced to about 19 000 by a quadplexing process. In case, moreover, one SPC having a function of sixteen taps is used, the number can be reduced to about 13 000 by an octaplexing process. Here, the reason why the number of elements is not halved even if the number of the SPCs is halved is that the number of elements to be used in control circuits, memories and so on increases.
Inventors
- 👤 Toru Hitachi Suzukishinden Baji
- 👤 Tatsuji Hitachi Kitanohara Matsuura
- 👤 Toshiro Tsukada
- 👤 Shinya Ohba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 00:06
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
260 words
A digital video signal processor comprising: (1) a first signal processing core (SPC1) for processing a plurality of digital video input signals, said first signal processing core having an M A1 number of arithmetic logic units (4) -and an M M1 number of multipliers (5); and (2) a second signal processing core (SPC2) having its input responding to the output of said first signal processing core for filtering it, said second signal processing core having an M A2 number of arithmetic logic units and an M M2 number of multipliers, wherein, in case: a sampling time shared between said two signal processing cores is desianated at T; the processing times of the arithmetic logic units (4) of said two signalprocessing cores (SPC1,SPC2) are designated at τ A1 and τ A2 , respectively; the processing times of the multipliers of said two signal processing cores are designated at τ M1 and τ M2 , respectively; the numbers of program steps of said two signal processing cores are designated P 1 and P 2 , respectively; the numbers of additions and subtractions are designated at N A1 and N A2' respectively; and the numbers of multiplications are designated at N M1 and N M2 , respectively, said digital video signal processor is time-multiplexed: - by using the minimum numbers M Ai and M Mi of said arithmetic logic units and said multipliers satisfying the following relations: and N Mi ≦ p i · M Mi (i = 1, 2) : and at the program step P i satisfying the following relations: and
Claim 2
Dependent Claim
260 words
A digital video signal processor comprising: (1) a first signal processing core (SPC1) for processing a plurality of digital video input signals, said first signal processing core having an M A1 number of arithmetic logic units (4) -and an M M1 number of multipliers (5); and (2) a second signal processing core (SPC2) having its input responding to the output of said first signal processing core for filtering it, said second signal processing core having an M A2 number of arithmetic logic units and an M M2 number of multipliers, wherein, in case: a sampling time shared between said two signal processing cores is desianated at T; the processing times of the arithmetic logic units (4) of said two signalprocessing cores (SPC1,SPC2) are designated at τ A1 and τ A2 , respectively; the processing times of the multipliers of said two signal processing cores are designated at τ M1 and τ M2 , respectively; the numbers of program steps of said two signal processing cores are designated P 1 and P 2 , respectively; the numbers of additions and subtractions are designated at N A1 and N A2' respectively; and the numbers of multiplications are designated at N M1 and N M2 , respectively, said digital video signal processor is time-multiplexed: - by using the minimum numbers M Ai and M Mi of said arithmetic logic units and said multipliers satisfying the following relations: and N Mi ≦ p i · M Mi (i = 1, 2) : and at the program step P i satisfying the following relations: and
Claim 3
Dependent Claim
36 words
A digital video signal processor as defined in Claim 1, wherein said each of said signal processing cores (SPC1, SPC2) has a phase locked loop (17 - 20) for generating a reference signal for instruction execution.
Claim 4
Dependent Claim
74 words
A digital video signal processor as defined in Claim 2, wherein said second signal processing core (SPC2) has delay circuits (6; 108, 109) each for delaying an input signal, a circuit for latching an external signal directly in said arithmetic logic units, a circuit for extracting the outputs of said arithmetic logic units directly to the outside, and means for setting the number of frequency divisions of a counter in said phase locked loop.
Claim 5
Dependent Claim
35 words
A digital video signal processor as defined in Claim 1, wherein said second signal processing core (SPC2) has its delay circuits (6; 108, 109) enabled to have their delay times set independently of one another.
References Cited (Backward Citations)
No citation records indexed.
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