EP0248606A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Submicron bipolar transistor with buried silicide region
Assignee: AT&T Inc
•
Filing: 1987-05-29
•
Granted: —
•
Expires: 2007-05-29
Abstract
Abstract A high performance bipolar transistor structure is disclosed which exhibits an extremely low extrinsic base resistance (r b ) by virtue of a silicide layer (26) which is included in the base contact portion of the structure. The silicide layer is situated to be electrically in parallel with the conventional heavily-doped polysilicon base contact region (24), where a vertical polysilicon runner (36ʹ) is used to provide a self-aligned electrical contact to the base. The parallel combination of the low resistivity (0.5-4 ohm/square) silicide with the polysilicon (sheet resistance of 10- 100 ohm/square) results in a low extrinsic base resistance on the order of 0.5-4 ohm/square. The disclosed device also includes a sub-micron emitter size, defined by vertical oxide sidewalls (40ʹ) above the base region (42), which furth er improves the high frequency performance of the device.
Inventors
- 👤 Anatoly Feygenson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 14:22
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D10/421; H10D64/00; H10D64/20; H10D64/27; H10D64/281; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/416
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
319 words
A high performance bipolar transistor structure comprising a monocrystalline silicon body (10) of a first conductivity type; a buried collector region (12) of a sec ond conductivity type formed in a top major surface of said body; an eptaxial layer (14) of said second conductivity type disposed over said top major surface (11) of said body; a deep collector contact region (20) formed in said epitaxial layer which connects said buried collector region to the top major surface (15) of said epitaxial layer; a base region (38) of said first conductivity type formed in the top major surface of said epitaxial layer above said buried collector region and separated from said deep collector contact region; and an emitter region (42) of said second conductivity type formed within said base region and extending to said top major surface of said epitaxial layer wherein said base region including an intrinsic base region located below said emitter region and an extrinsic base region located extending from said major surface and adjacent to said emitter region; CHARACTERISED IN THAT the bipolar transistor structure further comprises a base contact region including an insulating layer (22) disposed over said top major surface of said epitaxial layer above said buried collector region and adjacent to said base region; a heavily doped polysilicon layer (24) of said first conductivity type disposed over said insulating layer; a silicide layer (26) disposed over said heavily doped polysilicon layer, wherein the resistance of said silicide layer is significantly less than the resistance of said polysilicon layer; and an undoped polysilicon region (36) forming a vertical connecting region adjacent to said insulating, polysilicon and silicide layers and extending to the top major surface of said extrinsic base region, said polysilicon region forming a vertical connection between said extrinsic base region and said polysilicon and silicide layers, wherein the combination of said polysilicon and silicide layers provides a low extrinsic base resistivity.
Claim 2
Dependent Claim
319 words
A high performance bipolar transistor structure comprising a monocrystalline silicon body (10) of a first conductivity type; a buried collector region (12) of a sec ond conductivity type formed in a top major surface of said body; an eptaxial layer (14) of said second conductivity type disposed over said top major surface (11) of said body; a deep collector contact region (20) formed in said epitaxial layer which connects said buried collector region to the top major surface (15) of said epitaxial layer; a base region (38) of said first conductivity type formed in the top major surface of said epitaxial layer above said buried collector region and separated from said deep collector contact region; and an emitter region (42) of said second conductivity type formed within said base region and extending to said top major surface of said epitaxial layer wherein said base region including an intrinsic base region located below said emitter region and an extrinsic base region located extending from said major surface and adjacent to said emitter region; CHARACTERISED IN THAT the bipolar transistor structure further comprises a base contact region including an insulating layer (22) disposed over said top major surface of said epitaxial layer above said buried collector region and adjacent to said base region; a heavily doped polysilicon layer (24) of said first conductivity type disposed over said insulating layer; a silicide layer (26) disposed over said heavily doped polysilicon layer, wherein the resistance of said silicide layer is significantly less than the resistance of said polysilicon layer; and an undoped polysilicon region (36) forming a vertical connecting region adjacent to said insulating, polysilicon and silicide layers and extending to the top major surface of said extrinsic base region, said polysilicon region forming a vertical connection between said extrinsic base region and said polysilicon and silicide layers, wherein the combination of said polysilicon and silicide layers provides a low extrinsic base resistivity.
Claim 3
Dependent Claim
53 words
A high performance bipolar transistor structure as defined in claim 1 wherein the base contact region further comprises a silicon nitride layer (28) disposed over said silicide layer so as to overhang said insulating, polysilicon, and silicide layers such that the polysilicon vertical connecting region is contained underneath the silicon nitride overhang region.
Claim 4
Dependent Claim
41 words
A high performance bipolar transistor structure as defined in claim 2 wherein the transistor further comprises an oxide region (40ʹ) diposed to form vertical sidewalls adjacent to vertical polysilicon region, said oxide region defining the outer boundaries of the emitter region.
Claim 5
Dependent Claim
29 words
A high performance bipolar transistor structure as defined in claim 3 wherein the emitter region is formed using ion implantation within the boundaries defined by said vertical oxide region.
Claim 6
Dependent Claim
24 words
A high performance bipolar transistor structure as defined in claim 3 or claim 4 wherein the oxide layer comprises a low temperature oxide material.
Claim 7
Dependent Claim
28 words
A high performance bipolar transistor structure as defined in any of the preceding claims wherein the first conductivity is p-type conductivity and the second conductivity is n-type conductivity.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.