Digital reverberation system

Claim 2

A signal processor comprising, a closed network formed of lossless digital waveguides, a signal-scattering junction connected to said closed network, input/output means for providing signals to and from from said junction.

Claim 3

The signal processor of Claim 1 forming a lossless reverberator, said processor having one or more loss means for introducing loss factors of the form 1-2 -n to signal from said waveguides to set the reverberation decay time.

Claim 4

A digital signal processor for synthesizing a sound comprising, control variable means for providing a digital control variable for controlling the generation of said sound; a balanced digital waveguide unit including a first rail having a first delay for conducting signals in one direction, and including a second rail having a second delay for conducting signals in the opposite direction of said first direction, said second delay substantially equal to said first delay, junction means connecting the first rail to the second rail whereby said second rail conducts, at least in part, the same signals as said first rail; digital non-linear exciter means connected to receive said control variable signal and to receive an output from said second rail and to provide an input to said first rail whereby the signals conducted along _said first and second rails represent said sound.

Claim 5

A digital signal processor for synthesizing a sound comprising, control variable means for providing a digital control variable for controlling the generation of said sound; a balanced digital waveguide unit including a first rail having a first delay for conducting signals in one direction, and including a second rail having a second delay for conducting signals in the opposite direction of said first direction, said second delay substantially equal to said first delay, junction means connecting the first rail to the second rail whereby said second rail conducts, at least in part, the same signals as said first rail; digital non-linear exciter means connected to receive said control variable signal and to receive an output from said second rail and to provide an input to said first rail whereby the signals conducted along _said first and second rails represent said sound.

Claim 6

The processor of Claim 3 wherein said non-linear exciter includes a table for providing coefficients in response to said control variable.

Claim 7

The processor of Claim 4 wherein said table stores compressed coefficients g(x) at addresses x where g(x) is equal to f(x)/x, means for addressing said table with x to access g(x) from said table, means for multiplying g(x) by x to thereby form f(x).

Claim 8

The processor of Claim 3 wherein said waveguide is a pipelined balanced waveguide including a first rail having a delay section Z -2T forming an input to a junction, k i-1 (t-T/2), in turn connected to a junction K i (t+T/2), in turn connected to a delay Z and having a second rail connecting a delay Z -2T to a junction K i+1 (t-T/2) in turn connected to a junction K i (t+T/2) in turn connected to a delay Z -2T .

Claim 9

The signal processor of Claim 3 wherein said junction means is a 3-multiply normalized waveguide junction.

Claim 10

The signal processor of Claim 4 wherein said table provides coefficients k as a function of whereby said signal processor simulates a reed instrument.

Claim 11

The signal processor of Claim 4 wherein said table provides coefficients as a function of whereby said signal processor simulates a string instrument.

Claim 12

A signal processor comprising waveguide means including a first rail having a first delay for conducting first-rail signals in one direction, including a second rail having a second delay for conducting second-rail signals in the opposite direction of said first direction, said second delay substantially equal to said first delay, junction means connecting the first rail to the second rail and the second rail to the first rail whereby said first and second rails conduct, at least in part, the same signals, input means connected for inserting signals for conduction by said first and second rails, output means connected for receiving signals conducted by said waveguide means.

Claim 13

A signal processor comprising waveguide means including a first rail having a first delay for conducting first-rail signals in one direction, including a second rail having a second delay for conducting second-rail signals in the opposite direction of said first direction, said second delay substantially equal to said first delay, junction means connecting the first rail to the second rail and the second rail to the first rail whereby said first and second rails conduct, at least in part, the same signals, input means connected for inserting signals for conduction by said first and second rails, output means connected for receiving signals conducted by said waveguide means.

Claim 14

The signal processor of Claim 10 wherein said junction means further includes, a first rail adder providing a first-rail output signal, first and second first rail means receiving said first-rail and second-rail signals, respectively, and providing first and second first-rail adder input signals to said first-rail adder whereby said first-rail output signal is a function of said first-rail and second-rail signals, second-rail adder means providing a second rail output signal, first and second second-rail means receiving said first-rail and second-rail signals, respectively, and providing first and second second-rail adder input means whereby said second-rail output signal is a function of said 'first-rail and second-rail signals.

Claim 15

The processor of Claim 11 wherein said first and second first-rail means are first and second first-rail multipliers and wherein said first and second second-rail -means are first and second second-rail multipliers.

Claim 16

The processor of Claim 11 wherein said junction means has a first-rail input signal P -1 (t-T), has a second-rail input signal P (t), has a first-rail output signal P (t) and has a second-rail output signal P -1 (t+T), said junction including, a first multiplier for multiplying said first-rail input signal by g i (t) to form a first-rail multiplied signal, first subtractor means for subtracting said second-rail input signal from said first-rail multiplied signal to form a difference signal, second multiplier means for multiplying said difference signal by a factor to form a multiplied signal k i (t), first-rail adder means for adding said multiplied signal ki(t) to said first-rail multiplied signal to form said first-rail output signal, P (t), second-rail adder means for adding said multiplied signal K i (t) to said second-rail input signal P (t) to form a second-rail add signal, a multiplier for multiplying said second-rail add signal by the factor 1/g i (t) to form said second-rail output signal P -1 (t+T) where

Claim 17

The processor Claim 10 wherein said input means includes control variable means for providing a control variable for controlling the generation of said sound to simulate a reed instrument, wherein said junction means includes an inverter for inverting the signal from said first delay as an output from said first rail to provide an input to said second delay in said second rail, and wherein said non-linear exciter means generates waveguide coefficients for simulating reed pressure whereby said balanced waveguide simulates the bore of a reed instrument.

Claim 18

The processor of Claim 10 wherein said input means includes means for providing a control variable to control the generation of said sound as a bowed-string sound, wherein said balanced waveguide includes a first waveguide for simulating one portion of a string on one side of a bow, including a second waveguide for simulating the second part of the string on the other side of the bow, and wherein said junction means includes a first-waveguide first-adder for providing a first-rail input signal to said first waveguide, a' second-waveguide first-rail adder for providing a first-rail input signal to said second waveguide, first connection means for connecting the second-rail first-waveguide output as one input to said second-waveguide first-rail adder, second connection means for connecting said second-waveguide second-rail output as an input to said first-waveguide first-rail adder, and wherein said non-linear exciter means includes means for providing coefficients representing a bowed-string velocity to said first-waveguide first-rail adder and to said second-waveguide first-rail adder whereby said coefficients are added to provide an input to said first and second waveguides.

Claim 19

The processor of Claim 15 wherein said non-linear exciter includes means for the summing said first-waveguide second-rail output signal and said second-waveguide second-rail output signal to form a summed second-rail output signal, means for subtracting said second-rail summed signal from said control variable to provide a memory address, an addressable table for storing coefficients, means for addressing said table with said memory address to produce said control variable coefficients.

Claim 20

The processor of Claim 14 wherein said reed instrument is a saxophone, wherein said balanced waveguide includes a plurality of waveguide sections with each section separated from an adjacent section by a scattering junction, each said scattering junction having means for connecting at least a portion of the first-rail signal into said second rail and means for connecting at least a portion of said second rail signal into said first rail, said plurality of waveguide sections terminated in termination means.

Claim 21

The processor of Claim 17 wherein said termination means includes a low-pass filter to low-pass filter said first-rail output signal to provide an input to said second rail.

Claim 22

The processor of Claim 17 wherein said termination means includes DC blocking means for connecting first-rail output signals as inputs to said second rail.

Claim 23

The processor of Claim 17 wherein said termination means includes loss means for inserting a loss in said first-rail output signal so as to provide a loss in the first-rail output signal prior to connection as an input to said second-rail.

Claim 24

The processor of Claim 20 wherein said loss means is a digital multiplier for multiplying by a loss factor, g, where g is some value less than one.

Claim 25

The signal processor of Claim 10 wherein said input means provides a signal to be reverberated, wherein said waveguide means includes a plurality, i, of waveguide sections connected in parallel between first and second junctions forming first-rail output signals, P , and second rail output signals, Ri, said first node including means for summing the first-rail output signals, P , to form a first-rail summed signal, PI, and including means for connecting said first-rail summed signal as an input to said second rail for each of said waveguide sections, and wherein said second junction includes means for summing said second-rail output signals, R , to form a summed second-rail output signal, R I , and including means for connecting said second-rail summed signal as an input to said first-rail inputs for each of said sections.

Claim 26

The processor of Claim 17 wherein said input means provides an input signal to at least one of said waveguide sections for reverberation, where one or more of said waveguide sections includes a first-rail lossless delay and a second-rail lossless delay, means for introducing a loss into the signals in one or both of said first rail or second rail, first-rail adder means for adding a second-rail output signal from said second-rail delay to a first-rail input signal to provide an input to said first rail, second-rail adder means for adding a second-rail input signal to a first-rail output signal to provide a second-rail input signal, multiplier means for multiplying said first-rail output signal, P , by a factor a. to form the output signal α i P , second-rail multiplier means for multiplying said second-rail output signal, R by α i to form said output signal α i R , whereby said second junction forms the sum P as follows: and whereby said second junction forms the sum, R I ,

Claim 27

The processor of Claim 18 wherein 0≤α i ≤2 for each value of i and wherein R I ≤2 and Pi≤2 whereby a lossless digital reverberator is formed.

Claim 28

2 5 . The processor of Claim 10 wherein said waveguide means includes cascaded waveguides connected by one or more junctions and wherein said junctions includes means for introducing time-varying signals into said waveguide means.

Claim 29

The signal processor of Claim 10 wherein said waveguide means includes first and second junctions and includes a plurality of waveguides connected in parallel between said junctions.

Claim 30

The signal processor of Claim 26 wherein said waveguides are paired such that the delay in one waveguide of the pair is related to the delay in the other waveguide of the pair.

Claim 31

The signal processor of Claim 27 wherein the sum of the delays in all of said waveguides is less than 2.

Claim 32

The signal processor of Claim 10 wherein said junction means is a reflection free port.

Claim 33

The signal processor of Claim 10 where said junctions means includes a junction connecting to a plurality of waveguides - where each waveguide has a characteristic impedance and where the sum of all of the characteristic impedances for the waveguides connected to said junction sums to a constant.

Claim 34

The signal processor of Claim 30 wherein said constant is 2.

Claim 35

The signal processor of Claim 10 wherein said junction means includes a junction having at least one free port not connected to a waveguide, whereby said free port simulates a tone hole.

Claim 36

The signal processor of Claim 10 wherein said waveguides include one or more delays in combination with an all-pass filter.

Claim 37

The signal processor of Claim 10 wherein said waveguide means includes a plurality of cascaded waveguides, and wherein successive waveguides simulate the non-linear bore of an instrument.

Claim 38

The signal processor of Claim 4 wherein said table provides coefficients having magnitudes which range between zero and one.

Claim 39

The signal processor of Claim 10 wherein said input means includes means for receiving a control variable and includes means for modulating said control variable with a modulating signal.

Claim 40

The signal processor of Claim 36 wherein said signal processor includes means for providing said modulation signal as white noise.

Claim 41

The signal processor of - Claim 36 wherein said modulation signal is sinusoidal in form.