EP0248445A2
Expired / Lapsed
EP
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Semiconductor device having a diffusion barrier and process for its production
Assignee: Hitachi Ltd
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Filing: 1987-06-05
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Granted: —
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Expires: 2007-06-05
Abstract
Abstract This invention provides a semiconductor device having an electrode conductor layer (6) on a semiconductor substrate (1) through the medium of a diffusion barrier layer (5) which is formed of an amorphous material having a higher crystallization temperature than the heat treatment temperature for the semiconductor device, and a process for manufacturing this device. According to this invention, an undesired reaction between the metal of the electrode conductor layer (6) and the material of the semiconductor substrate (1) and the diffusion of the electrode conductor material into the semiconductor substrate (1) can be prevented, whereby a semiconductor device having a high thermal reliability can be obtained.
Inventors
- 👤 Yasushi Koubuchi
- 👤 Jin Onuki
- 👤 Masahiro Koizumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 03:58
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
83 words
A semiconductor device comprising a semiconductor substrate (1) having integrated circuits therein, a diffusion barrier layer (5) formed on said substrate, and an electrode conductor layer (6) formed of aluminum or an aluminum-silicon alloy on said diffusion barrier layer (5), characterized in that the diffusion barrier layer (5) is formed of an amorphous material having a crystallization temperature which is higher than the temperature of the heat treatment applied to the semiconductor device after formation of the electrode conductor layer (6) (Fig. 1).
Claim 2
Dependent Claim
83 words
A semiconductor device comprising a semiconductor substrate (1) having integrated circuits therein, a diffusion barrier layer (5) formed on said substrate, and an electrode conductor layer (6) formed of aluminum or an aluminum-silicon alloy on said diffusion barrier layer (5), characterized in that the diffusion barrier layer (5) is formed of an amorphous material having a crystallization temperature which is higher than the temperature of the heat treatment applied to the semiconductor device after formation of the electrode conductor layer (6) (Fig. 1).
Claim 3
Dependent Claim
38 words
The semiconductor device according to claim 1, characterized in that the diffusion barrier layer (5) is formed of an amorphous material having a crystallization temperature which is higher than the melting temperature of the electrode conductor material used.
Claim 4
Dependent Claim
25 words
The semiconductor device according to claim 1 or 2, characterized in that the diffusion barrier layer (5) has a thickness of 0,003 to 0,3 u.m.
Claim 5
Dependent Claim
62 words
The semiconductor device according to one of claims 1 to 3, characterized in that the amorphous material of the diffusion barrier layer (5) is an alloy, or a compound, of at least two metals selected from beryllium, boron, silicon, titanium, manganese, iron, cobalt, nickel, copper, yttrium, zirconium, niobium, molybdenum, ruthenium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, thorium, samarium, gadolinium, and terbium.
Claim 6
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous cobalt-10 to 30 atomic % titanium alloy.
Claim 7
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous copper-15 to 50 atomic % titanium alloy.
Claim 8
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous iron-5 to 20 atomic % zirconium alloy.
Claim 9
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous iron-60 to 80 atomic % zirconium alloy.
Claim 10
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous hafnium-50 to 70 atomic % cobalt alloy.
Claim 11
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous hafnium-50 to 70 atomic % nickel alloy.
Claim 12
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous titanium-15 to 35 atomic % nickel alloy.
Claim 13
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous zirconium-5 to 12 atomic % cobalt alloy.
Claim 14
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous zirconium-10 to 50 atomic % nickel alloy.
Claim 15
Dependent Claim
29 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous zirconium-30 to 80 atomic % palladium alloy.
Claim 16
Dependent Claim
34 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous titanium-24 to 55 atomic % beryllium-5 to 30 atomic % zirconium alloy.
Claim 17
Dependent Claim
34 words
The semiconductor device according to one of claims 1 to 4, characterized in that the diffusion barrier layer (5) is an amorphous zirconium-15 to 45 atomic % beryllium-5 to 30 atomic % niobium alloy.
Claim 18
Independent Claim
180 words
A method for manufacturing the semiconductor device according to one of claims 1 to 16, comprising the following principal steps: (A) providing a semiconductor substrate (1), (B) providing the respective doped regions (2, 3) of desired conductivity type and impurity/dopant concentration corresponding to the desired integrated circuit structures (C) forming an insulating oxide film (4) on the surface of the semiconductor body including the desired contact holes, (D) depositing a diffusion barrier layer (5) on the insulating oxide film (4), (E) depositing an electrode conductor layer (6) consisting of aluminum or an aluminum-silicon alloy on the diffusion barrier layer (5), (F) eventually thereafter removing selected parts of the diffusion barrier layer (5) and the electrode conductor layer (6) until to reach the insulating oxide film (4), and (G) applying a heat treatment at a temperature below the melting temperature of the electrode conductor material, characterized in that in step (D) a diffusion barrier layer (5) consisting of an amorphous material is deposited, the crystallization temperature of which is higher than the temperature of the heat treatment applied in step (G).
Claim 19
Dependent Claim
19 words
The process according to claim 17, characterized in that a silicon semiconductor substrate (1) is used in step (A).
Claim 20
Dependent Claim
28 words
The process according to claim 17 or 18, characterized in that integrated circuits and/or large scale integrated circuits are provided in the semiconductor substrate (1) in steps (B).
Claim 21
Dependent Claim
24 words
The process according to one of claims 17 to 19, characterized in that the steps (B) are carried out according to a planar process.
Claim 22
Dependent Claim
26 words
The process according to one of claims 17 to 20, characterized in that the insulating oxide film (4) is formed in step (C) by thermal oxidation.
Claim 23
Dependent Claim
21 words
The process according to one of claims 17 to 21, characterized in that step (F) is carried out by dry etching.
Claim 24
Dependent Claim
36 words
23 ; The process according to one of claims 17 to 22, characterized in that the diffusion barrier layer (5) and/or the electrode conductor layer (6) are deposited in steps (D) and (E), respectively, by sputtering.
Claim 25
Dependent Claim
30 words
The process according to one of claims 17 to 23, characterized in that in step (D) the diffusion barrier layer (5) is deposited by vapor deposition or chemical vapor deposition.
Claim 26
Dependent Claim
54 words
The process according to one of claims 17 to 24, characterized in that in step (D) a combination of at least two of the following metals is used: beryllium, boron, silicon, titanium, manganese, iron, cobalt, nickel, zirconium, niobium, molybdenum, copper, yttrium, ruthenium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, thorium, samarium, gadolinium, and terbium.
Claim 27
Dependent Claim
36 words
The process according to one of claims 17 to 25, characterized in that in step (D) at least one of the following alloys is used: Co-Ti Cu-Ti Fe-Zr Hf-Co Hf-Ni Ti-Ni Zr-Co Zr-Ni Zr-Pd Ti-Be-Zr Zr-Be-Nb.
Claim 28
Dependent Claim
144 words
The process according to claim 26, characterized in that in step (D) at least one of the following alloys is used in the indicated compositions (atomic %): Co - 10 - 30 % Ti Cu - 15 - 50 % Ti Fe - 5 - 20 % Zr Fe - 60 - 80 % Zr Hf - 50 - 70 % Co Hf - 50 - 70 % Ni Ti - 15 - 35 % Ni Zr - 5 - 12 % Co Zr - 10 - 50 % Ni Zr - 30 - 80 % Pd Ti - 24 - 55 % Be - 5 - 30 % Zr Zr - 15 - 45 % Be - 5 - 30 % Nb. 28. The process according to one of claims 17 to 27, characterized in that in step (D) eutectic compositions are applied.
Claim 29
Dependent Claim
99 words
The process according to claim 28. characterized in that in step (D) at least one of the following metal alloys or compounds is used in the indicated eutectic compositions (atomic %): Co - 22 % Ti Cu - 30 % Ti Fe - 10 % Zr Fe - 76 % Zr Hf - 67 % Co Hf - 67 % Ni Ti - 25 % Ni Zr - 8 % Co Zr - 24 % Ni Zr - 50 % Pd Ti - 40 % Be - 10 % Zr Zr - 30 % Be - 10 % Nb.
Claim 30
Dependent Claim
31 words
The process according to one of claims 17 to 29, characterized in that in step (D) the diffusion barrier layer (5) is deposited in a thickness of 0,003 to 0,3 µm.
References Cited (Backward Citations)
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