EP0248436A2
Expired / Lapsed
EP
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Method of and apparatus for processing data
Assignee: Hitachi Ltd
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Filing: 1987-06-04
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Granted: —
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Expires: 2007-06-04
Abstract
Abstract A data processor of this invention specifies (16,17) either of a predetermined maximum length of an address (a bits) and the length of an address less than the former length and at least one register (7) having the number or length of bits of the maximum address length or greater (r bits). The data processor reads out lower-order d bits of said at least one register (7) specified by a first instruction to perform arithmetic operations, and writes the arithmetic result into a register element contained in said at least one register (7). Moreover, the processor reads out bits from a register element contained in said at least one register (7) specified in a second instruction to generate an a-bit address, and reads out d bits from a storage device (5) in response to the thus-generated address to write the d bits into either the storage device (5) or said register element. Accordingly, since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address. Facilitating extension of the length of a storage address and assuring compatibility with conventional data processor.
Inventors
- 👤 Toyohiko Kagimasa
- 👤 Yoshiki Matsuda
- 👤 Kikuo Takahashi
- 👤 Seiichi Yoshizumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 22:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F9/30003; G06F9/30007; G06F9/30036
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
393 words
A data processor, comprising: a main storage (5); means (16, 17) for specifying address length selected from first bit length (a bits) and at least one second bit length shorter than the first bit length; a plurality of registers (7) each of third bit length (r bits) not shorter than the first bit length; operation means (8, 9, 10, 11) connected to said registers and said main storage for performing one of arithmetic or logical operations designated by an instruction on a first data signal held by a first one of the registers designated by the instruction or held by said main storage so as to provide a second data signal corresponding to the result of the one operation to a second one of the registers designated by the instruction or to said main storage, wherein both a bit portion which receives the one operation within the first data signal and a significant bit portion of the second data signal are not shorter than the first bit length (a bits) in a first mode of operation of said operation means and is equal to fourth bit length (d bits) shorter than the first bit length in a second mode of operation of said operation means; access means (4, 20, 21) connected to said main storage, said registers and said specifying means for generating an address having the first bit length in response to a bit portion with the specified address length within a third data signal held by a third one of the registers designated by an instruciton and accessing said main storage with the generated address, said access means including means for accessing said main storage for a'data signal having at least the first bit length in a first mode of operation thereof and having the fourth bit length in a second mode of operation thereof, so that a data signal of different length of a significant bit portion is transferred between said main storage and one of said operation means and said registers; control means (2, 13, 14) connected to said arithmetic means and said main storage means and responsive to an instruction requiring execution of an operation by said arithmetic means for controlling a mode of operation thereof and responsive to an instruction requiring access to said main storage by said access means for controlling a mode of operation thereof.
Claim 2
Dependent Claim
393 words
A data processor, comprising: a main storage (5); means (16, 17) for specifying address length selected from first bit length (a bits) and at least one second bit length shorter than the first bit length; a plurality of registers (7) each of third bit length (r bits) not shorter than the first bit length; operation means (8, 9, 10, 11) connected to said registers and said main storage for performing one of arithmetic or logical operations designated by an instruction on a first data signal held by a first one of the registers designated by the instruction or held by said main storage so as to provide a second data signal corresponding to the result of the one operation to a second one of the registers designated by the instruction or to said main storage, wherein both a bit portion which receives the one operation within the first data signal and a significant bit portion of the second data signal are not shorter than the first bit length (a bits) in a first mode of operation of said operation means and is equal to fourth bit length (d bits) shorter than the first bit length in a second mode of operation of said operation means; access means (4, 20, 21) connected to said main storage, said registers and said specifying means for generating an address having the first bit length in response to a bit portion with the specified address length within a third data signal held by a third one of the registers designated by an instruciton and accessing said main storage with the generated address, said access means including means for accessing said main storage for a'data signal having at least the first bit length in a first mode of operation thereof and having the fourth bit length in a second mode of operation thereof, so that a data signal of different length of a significant bit portion is transferred between said main storage and one of said operation means and said registers; control means (2, 13, 14) connected to said arithmetic means and said main storage means and responsive to an instruction requiring execution of an operation by said arithmetic means for controlling a mode of operation thereof and responsive to an instruction requiring access to said main storage by said access means for controlling a mode of operation thereof.
Claim 3
Dependent Claim
203 words
A data processor according to claim 1, wherein said control means (2, 13, 14) includes means responsive to an instruction requiring execution of an operation by said operation means for controlling said operation means so as to perform the first or second mode of operation thereof, depending upon the instruction belongs to a first or second group of instructions respectively, at least when the specified address length is the first bit length and so as to perform the second mode of operation thereof at least when the specified address length is the second bit length and at the same time the instruction belongs to the second group of instructions and responsive to an instruction requiring access to said main storage by said access means for controlling said access means so as to perform the first or second mode of operation thereof depending upon whether the instruction belongs to the first or second group, respectively, at least when the sepcified address length is the first bit length and so as to perform the second mode of operation thereof at least when the specified address length is the second bit length and at the same time the instruction belongs to the second group of instructions.
Claim 4
Dependent Claim
125 words
A data processor according to claim 2, wherein said means included in said control means includes means reponsive to an instruction requiring execution of an operation by said operation means for controlling said operation means so as to perform the first or second mode of operation thereof, respectively, depending upon whether the instructions belongs to a first or second group of instructions, irrespective of length of the specified address length and responsive to an instruction requiring access to said main storage by said access means for controlling said access means so as to perform the first or second mode of operation thereof, respectively depending upon whether the instruction belongs to the first or second group of instructions, irrespective of length of the specified address length.
Claim 5
Dependent Claim
155 words
A data processor according to claim 2, wherein said means included in said control means includes means connected to said specifying means and responsive to an instruction requiring execution of an operation by said operation means for controlling said operation means so as to perform the first or second mode of operation thereof, respectively when the specified address length is the first bit length and the instruction belongs to a first group of instructions or when the specified address length is the second bit length or the instruction belongs to a second group of instructions and responsive to an instruction requiring access to said main storage for controlling said access means so as to perform the first or second mode of operation thereof, respectively when the specified address length is the first bit length or when the specified address length is the second bit length or the instruction belongs to a second group of instructions.
Claim 6
Dependent Claim
134 words
A data processor according to claim 1, wherein said operation means includes: first operation means (8) for performing one of a first group of arithmetic or logical operations on a bit portion at least with the first bit length within a data signal held by one of said registers or read out of said main storage and providing a data signal corresponding to the result of the one operation having the first bit length; second operation means (9) for performing one of a second group of arithmetic or logical operations on a bit portion with the fourth bit length within a data signal held by one of said registers or read out of said main storage and providing a data signal corresponding to the result of the one operation having the second bit length.
Claim 7
Dependent Claim
64 words
A data processor according to claim 5, wherein said operation means further includes means (10) connected to said second operation means for generating a data signal having bit length not shorter than the first bit length and including the data signal provided by said second operation means so as to provide the generated data signal to one of said registers to be stored thereinto.
Claim 8
Dependent Claim
45 words
A data processor according to claim 5 or 6, wherein said operation means further includes select means (11) connected to said first arithmetic means and said generating means for selectively tranferring one of data signals provided by said first operation means and said generating means.
Claim 9
Dependent Claim
82 words
A data processor according to claim 6, wherein the third bit length is longer than the first bit length; wherein bit length of- a data signal which receives an operation by said first operation means is equal to the third bit length and bit length of a data signal provided by said first operation means is equal to the third bit length; and wherein bit length of a data signal generated by said generating means is equal to the third bit length.
Claim 10
Dependent Claim
40 words
A data processor according to any of the claims 5 to 8, wherein a total number of the first group of arithmetic or logical operations is smaller than a total number of the second group of arithmetic or logical operations.
Claim 11
Dependent Claim
65 words
A data processor according to claim 1, wherein said operation means includes means for providing, as the second data signal corresponding to the result of the operation by said operation means, a data signal having predetermined bit length not shorter than the first bit length irrespective of whether the mode of operation by said operation means is the first or second mode of operation thereof.
Claim 12
Dependent Claim
41 words
A data processor according to claim 10, wherein bit length of a bit portion which receives an operation by said operation means in the first mode of operation thereof and the predetermined bit length is equal to the third bit length.
Claim 13
Dependent Claim
19 words
A data processor according to claim 11, wherein the third bit length is longer than the first bit length.
Claim 14
Dependent Claim
180 words
A data processor according to claim 11, wherein said main storage means includes means for performing a write or read operation for a data signal having the third bit length in the first mode of operation thereof and for a data signal having the fourth bit length in the second mode of operation thereof; wherein said operation means includes means (9, 10) for receiving, from said main storage, a data signal of the fourth bit length to be provided to one of the registers and for generating a data signal of the third bit length including the received data signal as a significant bit portion so as to provide the generated signal to said one register in the second mode of operation of said operation means; and wherein said access means includes means (20, 21) for receiving a data signal having the third bit length from said operation means and providing a data signal comprised of a significant bit portion having the fourth bit length to said main storage to be stored therein in the second mode of operation thereof.
Claim 15
Independent Claim
209 words
An apparatus for processing data comprising: means for specifying either of a predetermined maximum length of an address (a bits) and the length of an address less than said predetermined maximum length; at least one register having the length of a bit string (r bits) equal to or greater than said predetermined maximum length; a first arithmetic means for reading out lower-order d bits of said at least one register specified by a first instruction, performing arithmetic operations of said d bits, writing the result of said arithmetic operations into a register element contained in said at least one register; address generating means for reading a specified effective length of a bit string out of a register element contained in said at least one register specified by a second instruction, generating an a-bit address; means for reading d bits out of a storage device in response to said address generated by said address generating means, writing said d bits into either of said storage device and a specified register element contained in said at least one register; and control means for activating said first arithmetic means in response to a first kind of instruction and for activating said address generating means in response to a second kind of instruction.
Claim 16
Independent Claim
209 words
An apparatus for processing data comprising: means for specifying either of a predetermined maximum length of an address (a bits) and the length of an address less than said predetermined maximum length; at least one register having the length of a bit string (r bits) equal to or greater than said predetermined maximum length; a first arithmetic means for reading out lower-order d bits of said at least one register specified by a first instruction, performing arithmetic operations of said d bits, writing the result of said arithmetic operations into a register element contained in said at least one register; address generating means for reading a specified effective length of a bit string out of a register element contained in said at least one register specified by a second instruction, generating an a-bit address; means for reading d bits out of a storage device in response to said address generated by said address generating means, writing said d bits into either of said storage device and a specified register element contained in said at least one register; and control means for activating said first arithmetic means in response to a first kind of instruction and for activating said address generating means in response to a second kind of instruction.
Claim 17
Dependent Claim
49 words
The apparatus according to claim 1 or claim 14, wherein said first kind of instruction includes a first kind of arithmetic or logig instruction and a first kind of storage access instruction, a first storage access means being activated in response to said first kind of storage access instruction.
Claim 18
Dependent Claim
116 words
The apparatus according to claim 4 or claim 14, wherein said first kind of arithmetic means comprises means for writing the d-bit result of arithmetic operations to lower-order d bits of a register element contained in said at least one register and for writing "0"s into all bits other than said lower-order d bits of said register element, said means for effecting writing to either of said register element and said storage device comprising means for writing data read from said main storage device into lower-order d bits of a register element contained in said at least one register and for writing "0" into all bits other than said d bits other than said register element.
Claim 19
Dependent Claim
99 words
The apparatus according to Claim 1, wherein said at least one register includes general register elements only, and said apparatus further including: second arithmetic means for reading lower-order n bits upward from a bits of first general register element or elements specified by an arithmetic instruction to perform arithmetic operations on said n bits and for writing the result of arithmetic operations on said n bits into lower-order n bits of a second register element specified by said arithmetic instruction; and means disposed in said control means for activating said arithmetic means in response to a second arithmetic instruction.
Claim 20
Dependent Claim
60 words
The apparatus according to Claim 7, wherein, if the effective length equal to or less than d bits of the address of an operand is specified in response to said second kind of arithmetic operation, said control means activates said first arithmetic means while, if said effective length specified exceeds d bits, said control means activates said second arithmetic means.
Claim 21
Dependent Claim
106 words
The apparatus according to Claim 6 further comprising a second storage access means for effecting either of the reading of r bits out of said storage device in response to an address generated by said address generating means to write said r bits to said first general register element specified by a storage access instruction and the reading of r bits out of said first register element to write said r bits into said storage device, said storage access control means including means for activating a second main storage access means in response to a second kind of main storage access instruction indicative of address transfer.
Claim 22
Dependent Claim
68 words
The apparatus according to Claim 9, wherein, if the effective length equal to or less than d bits of the address of an operand is specified in response to said second kind of main access control means, said storage access control means activates said first storage access means while, if said effective length specified exceeds d bits, said storage access control means activates said second storage access means.
Claim 23
Independent Claim
225 words
A method of processing data adapted to data processors including at least one register having the length of a bit string (r bits) equal to or less than a predetermined maximum length of an address, comprising the step of specifying either of said predetermined maximum length of an address (a bits) and the length of an address less than said predetermined maximum length; the arithmetic step of reading out lower-order d bits of said at least one register specified by a first instruction to perform arithmetic operations of said d bits to write the result of said arithmetic operations into a register element contained in said at least one register; the address generating step of reading a specified effective length of a bit string out of a register element contained in said at least one register specified by a second instruction to generate an a-bit address; the write step of reading d bits out of a storage device in response to said address generated by said address generating means to write said d bits into either of said storage device and a specified register element contained in said at least one register; and the control step of activating said first. arithmetic means in response to a first kind of instruction and for activating said address generating means in response to a second kind of instruction.
Claim 24
Independent Claim
225 words
A method of processing data adapted to data processors including at least one register having the length of a bit string (r bits) equal to or less than a predetermined maximum length of an address, comprising the step of specifying either of said predetermined maximum length of an address (a bits) and the length of an address less than said predetermined maximum length; the arithmetic step of reading out lower-order d bits of said at least one register specified by a first instruction to perform arithmetic operations of said d bits to write the result of said arithmetic operations into a register element contained in said at least one register; the address generating step of reading a specified effective length of a bit string out of a register element contained in said at least one register specified by a second instruction to generate an a-bit address; the write step of reading d bits out of a storage device in response to said address generated by said address generating means to write said d bits into either of said storage device and a specified register element contained in said at least one register; and the control step of activating said first. arithmetic means in response to a first kind of instruction and for activating said address generating means in response to a second kind of instruction.
References Cited (Backward Citations)
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