EP0246666B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Serial data bus for different modes of operation (SCI, SPI and buffered SPI) and methods for a serial peripheral interface in a serial data bus
Assignee: Old Carco LLC
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Filing: 1987-05-22
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Granted: 1994-05-04
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Expires: 2007-05-22
Abstract
No abstract record available.
Inventors
- 👤 Frederick O.R. Miesterfeld
- 👤 Ronald E. Fassnacht
- 👤 John M. Mccambridge
- 👤 Jerry M. Nasiadka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 22:55
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/407; H04L12/413; H04L12/4135; G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213; H04L2012/40267; H04L2012/40273
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
481 words
A communication system for the transmission of data messages through a data bus (26) between two or more user microprocessors (22) coupled to the data bus, the user microprocessors being coupled to the data bus by a bus interface integrated circuit (24), the bus interface integrated circuit comprising: an arbitration detector (42); a collision detector (44); a bus driver (28); a bus receiver (30); a current source (34) and a current sink (36) to drive the logical condition of the bus in response to signals from the bus driver and the bus receiver of the bus interface integrated circuit associated with each user microprocessor on the bus, whereby said user microprocessors (22) have an interface port of the types: a (SCI) port, a (SPI) port and a buffered serial peripheral interface (BSPI) port along with a clock port and an input/output port, and said buffer (304) is connected between the interface port of the user microprocessor (22) and said series circuit; and an idle and control detector (54); the bus receiver (30) connected between the data bus (26) and the interface port of the user microprocessor (22) to receive data messages from the data bus to the user microprocessor; the idle and control detector (54) connected between the input/output port of the user microprocessor (22) and individually to the arbitration detector (42) and collision detector (44) to monitor the data bus (26) and detect when the data bus is idle and when the data bus is busy; the communication system being characterized by the bus interface integrated circuit (24) being able to receive data from a user microprocessor (22) configured for data communications in SCI, SPI or BSPI modes, the bus interface integrated circuit (24) further comprising: a mode select circuit (30) for controlling data and shift clock (SCK) signal flow into and out of the bus interface integrated circuit by responding to the particular interface of the user microprocessor and operating in accordance with that interface, SCI, SPI or BSPI; a buffer (304); a SCK selector (302) for directing data in a buffered SPI mode and for describing the source of the clock signal for the buffer (304); a SCK counter (303) to count SCK pulses from the user microprocessor; a byte counter (306) for counting the number of bytes received; a start/stop/shift clock (SCK) generator (301); a SPI clock generator (308) to generate SCK pulses to the user microprocessor and buffer (304); a SPI transmit scheduler (309) and controller to control when data from a user microprocessor is put onto the bus in the SPI or BSPI modes; and the series circuit formed by the connection of the start/stop/SCK generator (301), the arbitration detector (42), collision detector (44) and the bus driver (28) connected between the interface port of the user microprocessor (22) and the data bus (26) to transmit data from the user microprocessor to the data bus.
Claim 2
Dependent Claim
158 words
The communication system of claim 1 further comprising: a digital filter (210) connected between the bus receiver (30) and the SCI port of the user microprocessor (22) to filter out noise from the data messages before being processed by other parts of the bus interface integrated circuit; timing and synchronizing means to establish synchronizing and a baud rate timing signal for use by the arbitration detector, collision detector and idle detector comprising: a clock divider (201) to receive a clock pulse from the user microprocessor to generate a clock signal; a word counter (202) to accept the clock signal and present timing and synchronizing information to the arbitration detector (42) and to the collision detector (44); a start bit detector (200) to indicate when a start bit signal and level is present on the data bus; a framing error detector (204) to indicate when the stop bit level is not on the data bus at stop bit time.
Claim 3
Dependent Claim
28 words
The bus communication system of claim 1 or 2, further comprising: a break generator (403) to allow a user microprocessor to force a logical condition onto the bus.
Claim 4
Dependent Claim
44 words
The communication system of one of claims 1 to 3, further comprising: an over range latch (61) and over range detector (60) to detect when the voltage on the bus deviates from a predetermined voltage window and to indicate the deviation when it occurs.
Claim 5
Dependent Claim
45 words
The communication system of claim 4, further comprising: a test mode detector (401) to signal the mode select circuit (301) to pass data from the over range latch (61) to the user microprocessor (22) and to allow the user micropro-cessor to call for a reset.
Claim 6
Dependent Claim
217 words
In a communication system according to one of claims 1 to 5, a method of transmitting data in a SPI mode of operation in conjunction with a method of arbitrating data on the data bus comprising: checking to see whether the data bus (26) is idle, waiting if it is not; waiting for the bus to be idle for 2-bit time; placing a start bit on the data bus; waiting until the end of the start bit; clocking the user microprocessor (22); pulling data from the user microprocessor; placing the data from the user microprocessor onto the bus depending on a possible block from the arbitration or collision methods utilized by the bus interface IC; latching the data into the user microprocessor; waiting for the eighth falling edge of a clock signal; waiting for the occurrence of 1/2 bit time; placing a stop bit on the data bus; checking to see whether the user microprocessor wishes to transmit another byte; if the user microprocessor does not wish to transmit another byte, waiting for the occurrence of eleven idle times, and making another check to see whether the user microprocessor wishes to put more data on the data bus; and if the user microprocessor wishes to transmit another byte, return to the previous steps to transmit the data.
Claim 7
Dependent Claim
169 words
In a communication system according to one of claims 1 to 5, a method of receiving data in a SPI mode of operation in conjunction with a method of arbitrating data on the data bus comprising: watching for a start bit to appear on the data bus; waiting until the end of the start bit once a start bit appears on the bus; signaling the arbitration method to lock the bus interface IC from transmitting; latching data into the user microprocessor; waiting for the eighth falling edge of the clock signal and then counting 2-bit-times; receiving a stop bit and waiting for the end of the stop bit to occur; checking for the occurrence of another start bit on the data bus, repeating the previous steps to latch in more data if another start bit is on the data bus; waiting ten idle times if there is no other start bit on the data bus and signaling the arbitration means to unlock the bus interface IC from transmitting data.
Claim 8
Dependent Claim
260 words
In a communication system according to one of claims 1 to 5, a method of transmitting data in a buffered SPI mode of operation in conjunction with a method of arbitrating data on the data bus comprising: checking to see whether another user microprocessor with higher priority is already transmitting on the data bus, waiting if such is the case; if the data bus is available for transmission, receiving the data input from the user microprocessor; signaling the data bus that transmission is about to occur; checking to see whether a start bit is on the data bus, waiting at least two idle bit times if no start bit is on the data bus for generating a stop bit; sending a signal to the data bus indicating that the bus is busy; waiting for the end of the start bit to occur; sending out the data to the bus separated by start and stop bits if not blocked by arbitration/collision methods in the bus interface IC; locking out the user microprocessor from the buffer on the bus interface integrated circuit; waiting for the second stop bit to occur; arranging data in the buffer to get the first byte in, such that the most significant byte out to the user microprocessor will be sent first; locking out the bus interface integrated circuit from the buffer; waiting for the reading of the data; repeating the previous steps if more data is to be transmitted; waiting eleven bit times if the data transmission is complete; and releasing the bus to an idle condition.
Claim 9
Dependent Claim
266 words
In a communication system according to one of claims 1 to 5, a method of receiving data in a buffered SPI mode of operation in conjunction with a method of arbitrating data on the data bus comprising: waiting for a start bit to appear on the data bus; signaling other user microprocessors that the data bus is busy; waiting for the end of the start bit to occur; waiting for the data to be read, locking the buffer from the bus if the data has not been read and waiting for the bus to return to an idle state before rechecking to see whether a start bit has appeared on the data bus; if all of the data has been read into the buffer, clock the buffer; allow data and stop bit to enter the data bus; allowing the user microprocessor to clock the buffer; waiting for the end of the stop bit; waiting for the occurrence of the start bit on the data bus before reading the rest of the data from the bus, but releasing the data bus to an idle condition if ten idle bit times follow the first entry of data; waiting for the stop bit time to occur and waiting for the end of the stop bit; checking to see whether a start bit has appeared on the bus and repeating the above procedures if more transmission is to occur; waiting for ten idle bit times if a start bit is not on the bus and signaling the rest of the user microprocessors that the bus is in an idle condition.
References Cited (Backward Citations)
No citation records indexed.
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