EP0246458A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Module for packaging semiconductor integrated circuit chips on a base substrate
Assignee: International Business Machines Corp
•
Filing: 1987-04-22
•
Granted: —
•
Expires: 2007-04-22
Abstract
Abstract An integrated circuit chip packaging structure, preferably having a semiconductor base substrate (1), i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers (8) being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power (39, 40) and signal lines (19, 20), with at least one power (16) or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.
Inventors
- 👤 Scott Laurence Jacobs
- 👤 Perwaiz Nihal
- 👤 Burhan Ozmat
- 👤 Henry Daniel Schnurmann
- 👤 Arthur Richard Zingher
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 22:14
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
59 words
An integrated circuit chip packaging structure characterized in that it comprises : a substrate; alternating insulation and conductive layers on said substrate; at least two of said conductive layers being patterned conductive layers having substantially coplanar spaced apart power and signal lines on each layer; interlayer connections between selected lines of at least two of said patterned conductive layers.
Claim 2
Dependent Claim
59 words
An integrated circuit chip packaging structure characterized in that it comprises : a substrate; alternating insulation and conductive layers on said substrate; at least two of said conductive layers being patterned conductive layers having substantially coplanar spaced apart power and signal lines on each layer; interlayer connections between selected lines of at least two of said patterned conductive layers.
Claim 3
Dependent Claim
27 words
The packaging structure of Claim 1 wherein each of said substantially coplanar signal lines are separated from each other by at least one substantially coplanar power line.
Claim 4
Dependent Claim
65 words
The packaging structure of Claim 1 or 2 wherein interlayer connections are made between a plurality of the power lines of a patterned conductive layer and a plurality of the power lines of another patterned conductive layer; the particular voltage level of any two interconnected power lines being the same; whereby at least one power plane at a particular voltage level exists in three dimensions.
Claim 5
Dependent Claim
84 words
The packaging structure of Claim 1, 2 or 3 further comprising a personalized conductive reference structure having a substantially planar upper surface; said reference structure having insulating regions extending at least partially through the body of said personalized reference structure at predetermined locations; said predetermined locations of said insulting regions coinciding with the locations of selected portions of the subsequent overlying patterned conductive layer; said reference structure being located above said base substrate and below a pair of patterned conductive layers in said package.
Claim 6
Dependent Claim
30 words
The packaging structure according to anyone of the preceding Claims wherein said insulation layers are formed of dielectric material selected from the group of organic dielectrics having active hydrogen atoms.
Claim 7
Dependent Claim
70 words
The packaging structure according to anyone of the preceding Claims wherein interlayer connections between two patterned conductive layers are completed by stepped conductive vias; said stepped conductive vias comprising a mound of dielectric material having metallization thereon; said metallization electrically interconnecting two patterned conductive layers. The packaging structure of Claim 15 wherein each of said coplanar signal lines are separated from each other by at least one coplanar power line.
Claim 8
Dependent Claim
44 words
The packaging structure according to anyone of the preceding Claims further comprising a grid of thin film metallization lines that are shorted together at each intersection of thin film lines; said grid being located above the uppermost patterned conductive layer in said packaging structure.
Claim 9
Dependent Claim
43 words
The packaging structure according to anyone of the preceding Claims wherein said substrate is selected from the group of silicon and gallium arsenide and said patterned conductive layers are made of thin film metallurgy lines having widths in the range of 2-15 microns.
Claim 10
Dependent Claim
58 words
The packaging structure according to anyone of the preceding Claims further comprising thin film metallurgy on areas substantially near the perimeter of selected conductive layers; said perimeter thin film metallurgy being selectively interconnected to other perimeter thin film metallurgy in said package and connected to at least one external power source; thereby forming power busses in said package.
Claim 11
Dependent Claim
29 words
The packaging structure according to anyone of the preceding Claims wherein said insulation layers are made of materials selected from the group of organic dielectrics having active hydrogen atoms.
Claim 12
Dependent Claim
14 words
The packaging structure of Claim 10 wherein said insulation layers are made of polyimide.
Claim 13
Dependent Claim
185 words
A packaging structure comprising: a substrate; alternating insulation and conductive layers on said substrate, the uppermost layer being a conductive layer; said insulation layers being formed of material selected from the group of organic dielectrics having active hydrogen atoms; at least two of said conductive layers being patterned conductive layers having substantially coplanar spaced apart power and signal lines on each layer; said power lines of each patterned conductive layer being substantially parallel to said signal lines on the same layer; each of said substantially coplanar signal lines being separated from each other by at least one substantially coplanar power line; stepped conductive vias comprising a dielectric mound having metallization thereon; said metallization electrically interconnecting selected portions of said patterned conductive layers; a personalized conductive reference structure having insulating regions extending at least partially through the body of said personalized reference structure at predetermined locations; said predetermined locations of said insulating regions coinciding with the locations of selected portions of the subsequent overlying patterned conductive layer; said reference structure being located above said substrate and below a pair of patterned conductive layers in said package.
Claim 14
Dependent Claim
185 words
A packaging structure comprising: a substrate; alternating insulation and conductive layers on said substrate, the uppermost layer being a conductive layer; said insulation layers being formed of material selected from the group of organic dielectrics having active hydrogen atoms; at least two of said conductive layers being patterned conductive layers having substantially coplanar spaced apart power and signal lines on each layer; said power lines of each patterned conductive layer being substantially parallel to said signal lines on the same layer; each of said substantially coplanar signal lines being separated from each other by at least one substantially coplanar power line; stepped conductive vias comprising a dielectric mound having metallization thereon; said metallization electrically interconnecting selected portions of said patterned conductive layers; a personalized conductive reference structure having insulating regions extending at least partially through the body of said personalized reference structure at predetermined locations; said predetermined locations of said insulating regions coinciding with the locations of selected portions of the subsequent overlying patterned conductive layer; said reference structure being located above said substrate and below a pair of patterned conductive layers in said package.
Claim 15
Dependent Claim
19 words
The packaging structure of Claim 12 wherein at least portions of the surface of said insulation layers are silylated.
Claim 16
Independent Claim
100 words
A method of forming an integrated circuit chip packaging structure having alternating insulation and patterned conductive layers on a semiconductor base substrate comprising; forming alternating insulation and conductive layers on a substrate; forming spaces at predetermined locations in at least one of said conductive layers; said spaces extending at least partially through said conductive layers; filling said spaces with insulation; patterning at least two of said conductive layers into a plurality of substantially coplanar, spaced apart lines, which are formed substantially parallel to each other; forming interlayer connections between selected lines of at least two of said patterned conductive layers.
Claim 17
Independent Claim
100 words
A method of forming an integrated circuit chip packaging structure having alternating insulation and patterned conductive layers on a semiconductor base substrate comprising; forming alternating insulation and conductive layers on a substrate; forming spaces at predetermined locations in at least one of said conductive layers; said spaces extending at least partially through said conductive layers; filling said spaces with insulation; patterning at least two of said conductive layers into a plurality of substantially coplanar, spaced apart lines, which are formed substantially parallel to each other; forming interlayer connections between selected lines of at least two of said patterned conductive layers.
Claim 18
Dependent Claim
65 words
The method of Claim 14 wherein at least one of said interlayer connections are formed by; forming a mound of dielectric material on an insulating layer; said mound being formed where interconnections between conductive layers are desired; forming patterned metallization over said insulation layer and at least one dielectric mound; whereby said metallization over each of said mounds interconnects lines of different patterned conductive layers.
Claim 19
Dependent Claim
42 words
The method of Claim 14 or 15 wherein said patterned conductive layers are formed by at least two metal deposition steps; each deposition of conductive lines overlaying the previous deposition; whereby opens and voids in the patterned conductive lines are substantially reduced.
Claim 20
Dependent Claim
34 words
The method of Claim 14, 15 or 16 further comprising silylating at least part of the surface of at least one of said insulation layers; thereby creating an etch barrier on said insulation layer.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.