EP0245882A2
Expired / Lapsed
EP
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Data processing system including dynamic random access memory controller with multiple independent control channels
Assignee: Advanced Micro Devices Inc
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Filing: 1987-03-05
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Granted: —
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Expires: 2007-03-05
Abstract
Abstract In a data processing system, a DRAM controller which is incorporated on a single semiconductor chip employs multiple column address strobe input signals that drive multiple column address strobe output signals respectively. The multiple signal channels for the column address strobe input signals and the column address strobe output signals are independent of each other and are each connected to a plurality of memory banks, but to different byte sections of the memory. Direct access to an individual byte of word-wide data is made possible.
Inventors
- 👤 Zwie Amitel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/22; G11C8/00; G11C8/12; G11C8/18; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/1056
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
128 words
A dynamic random access memory controller for providing address and control signals to memory banks comprising: means for providing address and control signals, including row address, column address, row address strobe and column address strobe signals; row address strobe driver means for receiving the row address strobe input signal and for producing a multiplicity of row address strobe output signals; column address strobe driver means for receiving a plurality of column address strobe input signals and for producing a like plurality of column address strobe output signals, the column address strobe input signals and column address strobe output signals being processed independently in separate channels; a multiplexer for selecting row address and column address signals and providing a multiplexed output of said row address and column address signals.
Claim 2
Dependent Claim
128 words
A dynamic random access memory controller for providing address and control signals to memory banks comprising: means for providing address and control signals, including row address, column address, row address strobe and column address strobe signals; row address strobe driver means for receiving the row address strobe input signal and for producing a multiplicity of row address strobe output signals; column address strobe driver means for receiving a plurality of column address strobe input signals and for producing a like plurality of column address strobe output signals, the column address strobe input signals and column address strobe output signals being processed independently in separate channels; a multiplexer for selecting row address and column address signals and providing a multiplexed output of said row address and column address signals.
Claim 3
Dependent Claim
52 words
A dynamic random access memory controller as in Claim 1, characterized by a bank latch coupled to the input of said row address driver means to provide a pair of bank select inputs that are strobed by said address latch strobe signal for enabling one of the row address strobe output signals.
Claim 4
Dependent Claim
36 words
A dynamic random access memory controller as in Claim 1, characterized by a timing generator for controlling the timing of said multiplexer and said column address strobe driver means, and said row address strobe driver means.
Claim 5
Dependent Claim
28 words
A dynamic random access memory controller as in Claim 1, characterized by a refresh counter coupled to the input of said multiplexer for incrementing a refresh address signal.
Claim 6
Dependent Claim
30 words
A dynamic random access memory controller as in Claim 1, characterized by means for operating said controller in a refresh mode, automatic access mode, or an externally controlled access mode.
Claim 7
Dependent Claim
26 words
A dynamic random access memory controller as in Claim 1, wherein said driver means, latch means and multiplexer are all formed on a single semiconductor chip.
Claim 8
Dependent Claim
33 words
A dynamic random access memory controller as in Claim 1, characterized by an output enable signal means for enabling said row address, column address, row address strobe and column address strobe output signals.
Claim 9
Dependent Claim
28 words
A dynamic random access memory controller as in Claim 1, characterized by a write enable signal means for enabling writing data at selected portions of said memory banks.
Claim 10
Dependent Claim
31 words
A dynamic random access memory controller as in Claim 1, characterized by latch means for passing said row address and column address signals in response to an address latch strobe signal.
Claim 11
Dependent Claim
105 words
A data processing system comprising: a multiplicity of random access memories, each memory having storage elements disposed in an array of rows and columns; a computer interface for providing address and control signals; characterized by a dynamic random access memory controller coupled to said interface and to said memories, including a column address strobe driver coupled to said interface for generating a like plurality of independent column address strobe output signals respectively for application to said memories in response to said column address strobe input signals; and means for coupling said plurality of column address strobe output signals independently to selected portions of said memories.
Claim 12
Dependent Claim
105 words
A data processing system comprising: a multiplicity of random access memories, each memory having storage elements disposed in an array of rows and columns; a computer interface for providing address and control signals; characterized by a dynamic random access memory controller coupled to said interface and to said memories, including a column address strobe driver coupled to said interface for generating a like plurality of independent column address strobe output signals respectively for application to said memories in response to said column address strobe input signals; and means for coupling said plurality of column address strobe output signals independently to selected portions of said memories.
References Cited (Backward Citations)
No citation records indexed.
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