EP0245783A2
Expired / Lapsed
EP
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Insulation method for integrated circuits, in particular with MOS and CMOS devices
Assignee: STMicroelectronics SRL
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Filing: 1987-05-07
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Granted: —
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Expires: 2007-05-07
Abstract
Abstract An insulation method integrated circuits, in particular with MOS and CMOS devices, reducing the minimum distance between the active regions up to the lithographic limit, regardless of the geometry of the field areas, comprises forming, in a semiconductor substrate, trenches having a reduced width, which delimit the active regions of the circuit and the extended field areas, filling the trenches with insulating material and local surface oxidating the field areas.
Inventors
- 👤 Paolo Giuseppe Cappelletti
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 10:13
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/011; H10W10/014; H10W10/0143; H10W10/0145; H10W10/0147; H10W10/10; H10W10/17; H10W10/40
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
59 words
An insulation method for integrated circuits, in particular with MOS and CMOS devices, characterized in that it comprises: - forming, in a semiconductor substrate, trenches having a reduced width and delimiting active regions of the circuit to be fabricated and wide field areas; - filling said trenches with insulating material; and - local surface oxidation of said field areas.
Claim 2
Dependent Claim
59 words
An insulation method for integrated circuits, in particular with MOS and CMOS devices, characterized in that it comprises: - forming, in a semiconductor substrate, trenches having a reduced width and delimiting active regions of the circuit to be fabricated and wide field areas; - filling said trenches with insulating material; and - local surface oxidation of said field areas.
Claim 3
Dependent Claim
15 words
A method according to claim 1, characterized in that said insulating material is deposited oxide.
Claim 4
Dependent Claim
15 words
A method according to claim 1, characterized in that said insulating material is polycrystalline silicon.
Claim 5
Dependent Claim
20 words
A method according to claim 1, characterized in that said trenches have a width ranging between 0.8 and 1.3 microns.
Claim 6
Independent Claim
24 words
A method according to one or more of the preceding claims, characterized in that said trenches have a minimum width obtainable with photolithographic methods.
Claim 7
Independent Claim
66 words
A method according to one or more of the preceding claims, characterized in that for filling said trenches an insulation layer is deposited above said semiconductor substrate, said insulation layer having a thickness comprised between 0.3 and 0.8/1,m, and said insulating layer is planarized by removing protruding portions of said insulating layer above said substrate, with said insulating material remaining only within said reduced width trenches.
Claim 8
Independent Claim
163 words
A method according to one or more of the preceding claims, characterized in that it comprises: - depositing a first uniform thin oxide layer on a semiconductor substrate; - depositing a first silicon nitride layer; - photolithographically depositing a first protection mask having windows at regions where trenches are to be formed; - etching said semiconductor substrate to form the trenches; - removing said first protective mask; - thermal oxidating a surface region of said semiconductor substrate at said trenches; - implanting enrichment boron at said wide field regions and at channel regions; - depositing a second oxide layer; - planarizating said second oxide layer; - removing said first silicon nitride layer; - depositing a third oxide layer; - depositing a second silicon nitride layer; - photolithographically depositing a second protection mask having windows at said wide field regions; - etching said second nitride layer; - removing said second protection mask; - thermal oxidating and removing remaining portions of said second nitride layer.
Claim 9
Dependent Claim
88 words
An integrated circuit, in particular MOS and CMOS interated circuit, comprising a semiconductor substrate having active regions and wide field regions, and an insulating layer (47 1 , 48, 51) extending on a face of said substrate, characterized in that said insulation layer has trench formations (47 1 ) with reduced width extending towards the interior of said substrate (40) and surrounding said active region and wide field regions and thermally oxidated, wide insulation portions (51) extending on said wide field regions and having extensions substantially equal thereto.
Claim 10
Dependent Claim
88 words
An integrated circuit, in particular MOS and CMOS interated circuit, comprising a semiconductor substrate having active regions and wide field regions, and an insulating layer (47 1 , 48, 51) extending on a face of said substrate, characterized in that said insulation layer has trench formations (47 1 ) with reduced width extending towards the interior of said substrate (40) and surrounding said active region and wide field regions and thermally oxidated, wide insulation portions (51) extending on said wide field regions and having extensions substantially equal thereto.
Claim 11
Dependent Claim
22 words
An integrated circuit according to claim 8, characterized in that said trench formations have a width ranging between 0.8 and 1.3 microns.
Claim 12
Dependent Claim
26 words
An integrated circuit, according to claim 8 or 9, characterized in that said wide insulation portions have a o depth ranging between 2500 and 4500 A.
References Cited (Backward Citations)
No citation records indexed.
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