EP0242854A2
Expired / Lapsed
EP
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Semiconductor memory devices
Assignee: Hitachi Ltd
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Filing: 1987-04-21
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Granted: —
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Expires: 2007-04-21
Abstract
Abstract In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory (1). Address information of a defective memory cell is stored as a reference data of the associative memory (1), and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory (1). For instance, a plurality of coincidence detection signal lines (16) of the associative memory (1) are divided into at least two groups, and one group among them is selected by switching means (5). Reference data of the associative memory (1) comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements (39).
Inventors
- 👤 Toshio Sasaki
- 👤 Masakazu Aoki
- 👤 Masashi Horiguchi
- 👤 Yoshinobu Nakagome
- 👤 Shinichi Ikenaga
- 👤 Toshiaki Masuhara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:05
CPC Classifications
G; G11; G11C; G11C17/00; G11C29/00; G11C29/70; G11C29/76; G11C15/00; G11C15/04; G11C15/046; G11C29/04; G11C29/08; G11C29/12; G11C29/44
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
69 words
A semiconductor memory device comprising: (1) a plurality of associative memory cells (31), each associative memory cell including a memory cell (39) that stores reference data, and a comparator (40) that compares said reference data with an inquiry data and that generates a coincidence detection signal from the output terminal thereof; and (2) a switch circuit (5) including at least first switching means (SW1) and second switching means (SW2);
Claim 2
Dependent Claim
69 words
A semiconductor memory device comprising: (1) a plurality of associative memory cells (31), each associative memory cell including a memory cell (39) that stores reference data, and a comparator (40) that compares said reference data with an inquiry data and that generates a coincidence detection signal from the output terminal thereof; and (2) a switch circuit (5) including at least first switching means (SW1) and second switching means (SW2);
Claim 3
Dependent Claim
116 words
wherein outputs of the comparators (40) of one group of said plurality of associative memory cells (31) are commonly connected to one end of said first switching means (SW1), outputs of the comparators (40) of the other group of said plurality of associative memory cells (31) are commonly connected to one end of said second switching means (SW2), and the other ends of said first and second switching means (SW1, SW2) are commonly connected to a coincidence detecting common line (16), and wherein the turn-on and the turn-off across said one ends and said other ends of said first and second switching means (SW1, SW2) are determined by the conditions of control terminals (36, 37) thereof.
Claim 4
Dependent Claim
116 words
wherein outputs of the comparators (40) of one group of said plurality of associative memory cells (31) are commonly connected to one end of said first switching means (SW1), outputs of the comparators (40) of the other group of said plurality of associative memory cells (31) are commonly connected to one end of said second switching means (SW2), and the other ends of said first and second switching means (SW1, SW2) are commonly connected to a coincidence detecting common line (16), and wherein the turn-on and the turn-off across said one ends and said other ends of said first and second switching means (SW1, SW2) are determined by the conditions of control terminals (36, 37) thereof.
Claim 5
Dependent Claim
38 words
The device of claim 1, wherein said switch circuit (5) further includes a flag memory (38) the output terminals of which are connected to said control terminals (36, 37) of said first and second switching means (SW1, SW2).
Claim 6
Dependent Claim
196 words
A semiconductor memory device comprising: (1) memory groups including a main memory and a spare memory which relieves fault portions of said main memory, said main memory having memory cells at crossings of a plurality of word lines and a plurality of data lines; (2) a word line converting circuit which supplies either one of a word line group external address or a new word line address, that is selected , to said memory groups; (3) a data line converting circuit which supplies either one of a data line group external address or a new data line address, that is selected, to said memory groups; and (4) circuit means which detects the coincidence of at least either one of said word line group external address or said data line group external address with at least a portion of addresses corresponding to faulty portions of the main memories, and which, based upon the detected result, supplies at least either one of the new word line address and the new data line address corresponding to an address of said spare memory to at least either one of said word line converting circuit or said data line converting circuit;
Claim 7
Dependent Claim
196 words
A semiconductor memory device comprising: (1) memory groups including a main memory and a spare memory which relieves fault portions of said main memory, said main memory having memory cells at crossings of a plurality of word lines and a plurality of data lines; (2) a word line converting circuit which supplies either one of a word line group external address or a new word line address, that is selected , to said memory groups; (3) a data line converting circuit which supplies either one of a data line group external address or a new data line address, that is selected, to said memory groups; and (4) circuit means which detects the coincidence of at least either one of said word line group external address or said data line group external address with at least a portion of addresses corresponding to faulty portions of the main memories, and which, based upon the detected result, supplies at least either one of the new word line address and the new data line address corresponding to an address of said spare memory to at least either one of said word line converting circuit or said data line converting circuit;
Claim 8
Dependent Claim
114 words
wherein said circuit means includes first memory means that stores faulty portions of said main memories as information that is divided into bit error, word line error and data line error, and wherein when said faulty portions are word line errors, said circuit means assumes the don't care condition for the data line address at the time when the address coincidence is detected based upon said information stored in said first memory means and when said faulty portions are data line errors, said circuit means assumes the don't care condition for the word line address at the time when the address coincidence is detected based upon said information stored in said first memory means.
Claim 9
Dependent Claim
114 words
wherein said circuit means includes first memory means that stores faulty portions of said main memories as information that is divided into bit error, word line error and data line error, and wherein when said faulty portions are word line errors, said circuit means assumes the don't care condition for the data line address at the time when the address coincidence is detected based upon said information stored in said first memory means and when said faulty portions are data line errors, said circuit means assumes the don't care condition for the word line address at the time when the address coincidence is detected based upon said information stored in said first memory means.
Claim 10
Dependent Claim
54 words
A semiconductor memory device according to claim 3, wherein said first memory means includes an associative memory, an address corresponding to said faulty portion is stored as reference data of the associative memory, and a new word line address and a new data line address are stored as output data of said associative memory.
Claim 11
Dependent Claim
36 words
A semiconductor memory device according to claim 3, further comprising a self test correction circuit which detects the presence of defective portion in said main memory and which relieves said defective portion using said spare memory.
Claim 12
Dependent Claim
33 words
A semiconductor memory device according to claim 4, wherein the reference data of said associative memory comprises three values consisting of binary information of "0" and "1", and a don't care value "X".
Claim 13
Dependent Claim
37 words
An associative memory device comprising: (1) associative memory cells for storing reference data; and (2) comparators which compare said reference data with an inquiry data and which produce a coincidence detection signal on the output terminals, thereof;
Claim 14
Dependent Claim
37 words
An associative memory device comprising: (1) associative memory cells for storing reference data; and (2) comparators which compare said reference data with an inquiry data and which produce a coincidence detection signal on the output terminals, thereof;
Claim 15
Dependent Claim
114 words
wherein said reference data comprises three values consisting of binary information of "0" and "1", and a don't care value "X", said associative memory cell includes a pair of binary flip-flops, a pair of outputs of said pair of flip-flops assume a first condition when the reference data "0" is being stored, the pair of outputs of said pair of flip-flops assume a second condition different from said first condition when the reference data "1" is being stored, and the pair of outputs of said pair of flip-flops assume a third condition different from said first condition or said second condition when the reference data of the don't care value "X" is being stored.
Claim 16
Dependent Claim
114 words
wherein said reference data comprises three values consisting of binary information of "0" and "1", and a don't care value "X", said associative memory cell includes a pair of binary flip-flops, a pair of outputs of said pair of flip-flops assume a first condition when the reference data "0" is being stored, the pair of outputs of said pair of flip-flops assume a second condition different from said first condition when the reference data "1" is being stored, and the pair of outputs of said pair of flip-flops assume a third condition different from said first condition or said second condition when the reference data of the don't care value "X" is being stored.
Claim 17
Independent Claim
116 words
A method of relieving defects of a semiconductor memory device, comprising: (1) a first step for arranging n (n > 1) main memories and m (m > 1) spare memories; (2) a second step which inspects whether there are defects at the same address of (m + 1) or greater main memories, and which, when the inspected result is yes, determines said n main memories to be not acceptable; and (3) a third step which, when the inspected result in said second step is no, inspects said n main memories successively in regard to if there are any defective bits and which, when the inspected result is yes, relieves said defective bits using the spare memories.
Claim 18
Independent Claim
116 words
A method of relieving defects of a semiconductor memory device, comprising: (1) a first step for arranging n (n > 1) main memories and m (m > 1) spare memories; (2) a second step which inspects whether there are defects at the same address of (m + 1) or greater main memories, and which, when the inspected result is yes, determines said n main memories to be not acceptable; and (3) a third step which, when the inspected result in said second step is no, inspects said n main memories successively in regard to if there are any defective bits and which, when the inspected result is yes, relieves said defective bits using the spare memories.
Claim 19
Dependent Claim
113 words
A method of relieving defects of a semiconductor memory device according to claim 8, wherein a fail bit memory which records defect/non-defect of memory cells of a main memory which is one of the objects among n main memories to be tested by said second step, is comprised of at least (2m + 1)memories which include main memories that are different from said objects to be tested and spare memories, the same data related to defect/non-defect of the mrmory cells is written onto said(2m + 1)memories that word as said fail bit memory, and the reading of said data is executed by the decision-by-majority of data read from said (2m + 1) memories.
Claim 20
Dependent Claim
41 words
A semiconductor memory device comprising: (1) a plurality of associative memory cells, each associative memory cell storing reference data and comparing the thus stored reference data with an inquiry data to produce a coincidence detection signal from the output terminal thereof;
Claim 21
Dependent Claim
41 words
A semiconductor memory device comprising: (1) a plurality of associative memory cells, each associative memory cell storing reference data and comparing the thus stored reference data with an inquiry data to produce a coincidence detection signal from the output terminal thereof;
Claim 22
Dependent Claim
21 words
wherein said reference data is stored in at least one electrically programable non-volatile semiconductor memory element in each associative memory cell.
Claim 23
Dependent Claim
21 words
wherein said reference data is stored in at least one electrically programable non-volatile semiconductor memory element in each associative memory cell.
Claim 24
Dependent Claim
32 words
A semiconductor memory device according to claim 10, wherein said electrically programable non-volatile semiconductor memory element comprises a floating gate-type non-volatile semiconductor memory element having source, drain, floating gate and control gate.
Claim 25
Dependent Claim
146 words
A semiconductor memory device according to claim 11, wherein each of said associative memory cells is constituted by two floating gate-type non-volatile semiconductor memory elements, drains of said two floating gate-type non-volatile semiconductor memory elements are commonly connected in each associative memory cell, the control gates thereof are connected to different signal lines, storage of the reference data in the associative memory cells is executed by the combination of high and low threshold voltages of said two floating-gate-type non-volatile semiconductor memory elements by applying signals to said drains and to said control gates, and comparison of the stored reference data with the inquiry data is executed by detecting the signal level of said commonly connected drains that changes depending upon the combination of conduction and nonconduction of said two floating gate-type non-volatile semiconductor memory elements in response to the application of signals to said signal lines.
Claim 26
Dependent Claim
37 words
A semiconductor memory device according to claim 12, further comprising a signal processing portion which generates output data consisting of a predetermined number of bits in response to the outputs of said plurality of associative memory cells.
Claim 27
Dependent Claim
64 words
A semiconductor memory device according to claim 13, wherein said signal processing portion includes a plurality of non-volatile semiconductor memory elements, and generates said output data consisting of said predetermined number of bits written onto said non-volatile semiconductor memory elements of said signal processing portion in response to a coincidence detection signal generated from at least one of said plurality of associative memory cells.
References Cited (Backward Citations)
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